Low capacitance interconnection

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438619, 438620, 438622, 438623, 438624, H01L 214763

Patent

active

061469858

ABSTRACT:
A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.

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