Low area architecture in BCH decoder

Details Low area architecture in BCH decoder Low area architecture in BCH decoder

2006-12-20

2010-10-26

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S752000, C714S758000, C714S781000

Reexamination Certificate

active

07823050

ABSTRACT:
An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X<(t+1), where t is a number of transmission errors for the key equation solver block to correct, and codeword_len is a length of a transmitted codeword to be decoded by the BCH decoder.

REFERENCES:
patent: 5323402 (1994-06-01), Vaccaro et al.
patent: 7467346 (2008-12-01), Hassner et al.
Kang et al., “A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure,” IEEE Intern., vol. 3, pp. 3180-3183, (2002).
Sarwate et al., “High-speed architectures for Reed-Solomon decoders,” IEEE transactions on VLSI Systems, vol. 1, No. 5, pp. 641-655, (2001).
Burton, “Inversionless Decoding of Binary BCH Codes,” IEEE Transactions on Information Theory, vol. IT-17, No. 4, pp. 464-466, (1971).

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