4. Static information storage and retrieval
  5. Read/write circuit
  6. Including specified plural element logic arrangement

Sergei Gashkov

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Low area architecture in BCH decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate

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RRAM flipflop rcell memory generator

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate

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Profile ID: LFUS-PAI-P-3052699

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