Loop-back method for measuring the interface timing of...

Details Loop-back method for measuring the interface timing of... Loop-back method for measuring the interface timing of...

2008-07-08

2008-07-08

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07398444

ABSTRACT:
The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.

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M. Gerner, B. Müller and G. Sandweg, Selbsttest digitaler Schaltungen (Self-test of Digital Circuits), München, Germany, R. Oldenbourg, 1990, pp. 74-82, 136, 137 and 140-151, ISBN 3-486-21765-8.

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