Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-02-11
2003-09-23
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100, C365S236000, C365S185250
Reexamination Certificate
active
06625078
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention pertains to, integrated circuit memories, and, more particularly, to row access speed and the interaction with the refresh function in an integrated circuit memory.
A refresh or active command can occur on any clock cycle in an integrated circuit memory, requiring internal (on-chip) detection of the cycle type being executed. This detection process slows down the row address path within the device.
On-chip refresh circuitry has been incorporated in DRAM designs for several decades. When first introduced, a separated refresh pin was used to inform the DRAM to execute a refresh operation, using internally generated addresses, instead of a normal externally supplied row address. Later, /CAS-before-/RAS (CAS=column address strobe, and RAS=row address strobe) commands were used to enable on-chip refresh cycles. When /CAS was high and /RAS went low, a normal row selection was done using the external address supplied to the time when /RAS went low. However, if /CAS was low when /RAS went low, then a refresh operation was executed using an internally generated refresh address.
Today, SDRAMs support two different types of refresh: auto-refresh and self-refresh. Auto-refresh uses a specific command instruction: /CS (chip select), /RAS, and /CAS low with /WE (write enable) high, that is sampled at the rising edge of the DRAM's input clock signal. Self-refresh command is similar to auto-refresh, but occurs concurrently with entering power-down mode. In self-refresh, the device periodically executes refresh cycles (self-timed) to maintain stored data integrity during power-down mode.
In the past, incorporating on-chip refreshing using the methods described above, had little impact on device performance. However, as the operating frequency of DRAMs and SDRAMs has increased, the inclusion of on-chip refreshing, using conventional methods, has had an impact on row access performance. With present methods, during any cycle that an active command can be executed, a refresh command could have been executed instead, provided the device had been previously idle (in precharge state.) For this reason, the on-chip circuitry must hold-off row selection while the appropriate address is selected, depending on whether the present instruction is an active or a refresh command. This process is complicated in most instances. A command address latch is used to hold either the externally supplied row address or the internally generated address from the refresh address counter depending on the command. As clock rate increases, the penalty due to selecting which address to use before row selection can be enabled will become a larger percentage of the row select time.
What is desired, therefore, is a circuit and method for enabling the refresh function in an integrated circuit DRAM without undesirably adding to row access time.
SUMMARY OF THE INVENTION
According to the present invention, a circuit and method for an integrated circuit memory overcomes the deficiency of having to delay enabling the row selection circuitry until the appropriate address source has been determined, based on each cycle command. The circuit and method of the present invention incorporates a look-ahead approach where refresh commands are presented to the device one clock cycle before actual internal initiation of refresh operations occur. Active commands are unaltered and are executed on the same clock cycle as the occurrence of the active command. In this way, active commands can be executed immediately without the need of waiting to determine if the row address latch is to be sourced externally or internally.
The present invention uses a look-ahead for the REFRESH command in the memory. The invention reduces Active cycle latency (time from ACTIVE command to when the selected row and sense amplifiers have been activated) while not impacting system cycle time, even though a new look-ahead refresh method is used. On any given clock cycle when an ACTIVE command is given, an address input is selected on the ACTIVE command clock cycle, without the need to wait for control logic determination of whether it is an ACTIVE or a REFRESH command. Conversely, the refresh counter is selected on the command clock cycle that refresh initiates, without the need to wait for control logic to determine whether it is an ACTIVE or a REFRESH command since the condition was predetermined via the REFRESH command executed on the prior clock cycle.
The major advantage of the present invention is that it defines a separation between refresh and active commands such that the device can pre-select the row address path without waiting for a cycle type detection process. The detection of cycle type is done via a look-ahead (early) refresh command.
It is another advantage that the method of the present invention allows for on-chip refreshing without penalizing non-refresh command performance.
It is another advantage of the present invention that the timing examples shown apply not only to standard SDRAM memories, but the invention and timing diagrams apply to embedded DRAM and specialty DRAM as well.
REFERENCES:
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patent: 6134167 (2000-10-01), Atkinson
patent: 6167484 (2000-12-01), Boyer et al.
patent: 6404689 (2002-06-01), Kirihata et al.
patent: 6411157 (2002-06-01), Hsu et al.
Hardee Kim C.
Jones, Jr. Oscar Frederick
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
Nguyen Viet Q.
United Memories Inc.
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