Logic-synthesis method and logic synthesizer

Details Logic-synthesis method and logic synthesizer Logic-synthesis method and logic synthesizer

2006-01-19

2008-11-04

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07448006

ABSTRACT:
The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes the steps of generating a library having a buffer-tree-characteristic description, determining the position where the fanout value is high by analyzing a logic-design description, specifying the configuration of a buffer tree including the high fanout position, and performing logic synthesis according to the logic-design description.

REFERENCES:
patent: 5864487 (1999-01-01), Merryman et al.
patent: 6910202 (2005-06-01), Minami et al.
patent: 7007263 (2006-02-01), Yang et al.
patent: 2002-312411 (2002-10-01), None
patent: 2004-62694 (2004-02-01), None

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