Logic synthesis for testability system which enables improvement

Details Logic synthesis for testability system which enables improvement Logic synthesis for testability system which enables improvement

1998-03-06

2000-05-30

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714718, 39550003, 39550005, 39550007, G01R 3128

Patent

active

060702583

ABSTRACT:
A logic synthesis for testability system including a testability improving unit which employs a center state of an FSM of a circuit as a target for logic synthesis to reduce a distance between predetermined states for improving testability of the circuit expressed by the FSM which is held in a storage unit, the testability improving unit including a center state candidate selecting unit for excluding an asynchronous reset state and a predetermined state with a short distance from the asynchronous reset state from center state candidates and a center state selecting unit for sequentially selecting states not excluded by the center state candidate selecting unit as center state candidates, thereby conducting optimization processing taking testability into consideration during logic circuit designing.

REFERENCES:
patent: 4720672 (1988-01-01), Turino
patent: 5097151 (1992-03-01), Eerenstein et al.
patent: 5228040 (1993-07-01), Agrawal et al.
patent: 5461573 (1995-10-01), Chakradhar et al.
patent: 5515292 (1996-05-01), Roy et al.
patent: 5877905 (1999-03-01), Hieter et al.
Frank F. HSU et al., "A Distance Reduction Approach to Design for Testability", 1995, pp. 158-163.

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