Logic product circuit

Details Logic product circuit Logic product circuit

2000-06-27

2002-05-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar and fet

C326S109000, C326S101000

Reexamination Certificate

active

06388473

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an LSI circuit, and in particular, to a CMOS or Bi-CMOS logic product circuit.
This application is based on Japanese Patent Application Nos. Hei 11-182513 and Hei 11-218204, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Of conventional logic product circuits comprising CMOSs or Bi-CMOSs, a four-input NAND circuit provides a transistor array in which four transistors are aligned in a line and are connected between output terminals of the four-input NAND circuit and GND.
The four input terminals of the four-input NAND circuit are connected to the inputs (gates) to four transistors. When signals at an H level are input to all the input terminals and all four transistors are turned on, the entire transistor array becomes conductive, the output terminals are connected to GND, and the output terminals are set to an L level. Thus, this circuit functions as a NAND circuit.
Other conventional four-input NAND circuits increase their electric current driving performance of their outputs by connecting a plurality of transistor arrays in parallel between the output terminals and GND. When an electric current is supplied at the same time to a certain number n of transistor arrays provided in parallel, n times the electric current output from the single transistor array can be gained.
The structure of the four-input NAND circuit will be explained with reference to FIG.
5
. In this figure, INA, INB, INC, and IND are inputs to the four-input NAND circuit, and OUT is an output from the four-input NAND circuit.
QP
51
, QP
52
, QP
53
, and QP
54
are P-channel transistors (hereinafter referred to as Pch transistors), and QN
51
, QN
52
, . . . , QN
59
, QN
5
A, QN
5
B, and QN
5
C are N-channel transistors (hereinafter referred to as Nch transistors).
The Pch transistors QP
51
to QP
54
are connected between a power source voltage Vdd and an output terminal OUT in a parallel manner. That is, the sources of QP
51
to QP
54
are connected to the power source voltage Vdd, and the drains of QP
51
to QP
54
are connected to the output terminal OUT. The gates of QP
51
to QP
54
are connected to four input terminals INA, INB, INC, and IND, respectively.
The Nch transistors QN
51
to QN
54
are connected in a line, forming a transistor array TA
51
. In the transistor array TA
51
, the source of QN
51
is connected to the drain of QN
52
, the source of QN
52
is connected to the drain of QN
53
, and the source of QN
53
is connected to the drain of QN
54
.
This transistor array TA
51
is connected between the output terminal OUT and GND. That is, the drain of QN
51
is connected to the output terminal OUT, and the source of QN
54
is connected to GND.
Similarly, the Nch transistors QN
55
to QN
58
form a transistor array TA
52
, which is connected between the output terminal OUT and GND. Further, the Nch transistors QN
59
to QN
5
C form a transistor array TA
53
, which is also connected between the output terminal OUT and GND.
The input terminals INA, INB, INC, and IND are connected to the gate terminals of the Pch transistors QP
51
, P
52
, QP
53
, and QP
54
, respectively.
When the input terminal INA is set to the L level, QP
51
is turned on and becomes conductive so that the source voltage Vdd is output from the output terminal OUT. Similarly, when the input terminals INB, INC, and IND are set to the L level, QP
52
, QP
53
, and QP
54
are turned on and become conductive so that the source voltage Vdd is output from the output terminal OUT. This output from the output terminal OUT is at the H level.
When a least one of the input terminals INA, INB, INC, and IND is set to the L level, a signal at the H level is output from the output terminal OUT.
The input terminal INA is connected to the gates of the Nch transistors QN
51
, QN
55
, and QN
59
which are the nearest to the output terminal OUT. The input terminal INB is connected to the gates of Nch transistors QN
52
, QN
56
, and QN
5
A. The input terminal INC is connected to the gates of Nch transistors QN
53
, QN
57
, and QN
5
B. The input terminal IND is connected to the gates of the Nch transistors QN
54
, QN
58
, and QN
5
C which are the nearest to GND.
When the input terminal INA is set to the L level and the input terminals INB, INC, and IND are set to the H level, the Nch transistors QN
51
, QN
55
, and QN
59
to which the input terminal INA is connected are turned off, the Nch transistors QN
52
, QN
56
, and QN
5
A to which the input terminal INB is connected, the Nch transistors QN
53
, QN
57
, and QN
5
B, and the Nch transistors QN
54
, QN
58
, and QN
5
C to which the input terminal IND is connected are turned on.
In this situation, because the transistor array TA
51
includes the Nch transistor QN
51
which has been turned off, the entire transistor array TA
51
has been turned off. Similarly, because the transistor array TA
52
includes the Nch transistor QN
55
which has been turned offOFF, the entire transistor array TA
52
has been turned off. Further, because the transistor array TA
53
includes the Nch transistor QN
59
which has been turned off, the entire transistor array TA
53
has been turned off.
Because the transistor arrays TA
51
, TA
52
, and TA
53
which are provided in parallel to each other between the output terminal OUT and GND have been turned off, the output terminal OUT is not connected to GND. Because the input terminal INA is at the L level, the Pch transistor QP
51
has been turned on so that the source voltage Vdd is connected to the output terminal OUT.
Accordingly, when the input terminal INA is set to the L level and the input terminals INB, INC, and IND are set to the H level, the output terminal OUT outputs a signal at the H level.
When all the input terminals INA, INB, INC, and IND are set to the H level, the Nch transistors QN
51
, QN
55
, QN
59
, QN
52
, QN
56
, QN
5
A, QN
53
, QN
57
, QN
5
B, QN
54
, QN
58
, and QN
5
C are turned on. That is, the transistor arrays TA
51
, TA
52
, and TA
53
become conductive so that the output terminal OUT is connected to GND. On the other hand, because all the input terminals INA to IND are at the H level, all the Pch transistors QP
51
to QP
54
have been turned off, and the source voltage Vdd is not connected to the output terminal OUT.
Accordingly, when all the input terminals INA, INB, INC, and IND are set to the H level, the output terminal OUT outputs a signal at the L level.
Next, the operation of this conventional art will be explained with reference to the operation timing chart of FIG.
6
. Before the point of time t
61
, because the input terminal INA is at the L level and INB to IND are at the H level, the output terminal OUT is at the H level.
At the point of time t
61
, when the input terminal INA is inverted from the L level to the H level while maintaining the input terminals INB to IND at the H level, that is, when all the input terminals INA to IND are set to the H level, the output terminal OUT varies from the H level to the L level in the period tpdA between t
61
and t
62
.
At the point of time t
63
, when the input terminal IND is inverted from the H level to the L level while maintaining the input terminals INA to INC at the H level, the output terminal OUT varies from the L level to the H level in the period tpdD between t
63
and t
64
.
At the point of time t
65
, when the input terminal IND is inverted from the L level to the H level while maintaining the input terminals INA to INC at the H level, the output terminal OUT varies from the H level to the L level in the period tpdD between t
65
and t
66
.
As another conventional technique, a five-input NAND circuit shown in the circuit diagram of
FIG. 7
is known. In this circuit, each of the transistor arrays TA
1
to TA
4
comprises five Nch transistors connected in a line. The gates of the five Nch transistors are connected to input terminals INA to INE, respectively.
FIG. 10
shows the layout of the circuit on an IC. On the IC, the transistor arrays TA
1
t

Affiliated with

Also associated with

Rating

Logic product circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic product circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic product circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2830015