Logic interface circuit and semiconductor memory device...

Details Logic interface circuit and semiconductor memory device... Logic interface circuit and semiconductor memory device...

2000-05-22

2001-10-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189080, C365S189090, C365S203000

Reexamination Certificate

active

06304495

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. 99-18503, filed on May 21, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface circuit, and more particularly to a logic interface circuit for shifting levels of supply voltages and a semiconductor memory device to which the logic interface circuit is applied, where the logic interface circuit uses logic gates such as inverter, a NAND gate, and a NOR gate.
2. Description of the Prior Art
In general, a level shifter is used for changing and outputting levels of input signals. That is, the level shifter is a circuit to change a CMOS level of a signal into a TTL level of a signal and output it, or vice versa
In case that two functional blocks inside a chip has different supply voltages, the level shifter as such can be used to interface between the two blocks. However, general level shifters are made with complicated structures, which increases the space required for the chip.
For example, a semiconductor memory device is constructed with a plurality of functional blocks. In order to improve the operational speed of the semiconductor memory device by making the levels of supply voltage different among the functional blocks, a level shifter should be additionally provided between those different functional blocks. In other words, if at least more than two supply voltages are applied to the semiconductor device, a level shifter should be added to interface between those functional blocks which have different supply voltages.
However, if the level shifter as such is added to the chip, the circuit of the semiconductor memory device becomes complicated, thereby increasing the area for the chip.
SUMMARY OF THE INVENTION
Therefore, the present invention is presented to solve the aforementioned problem. It is an object of the present invention to provide a logic interface circuit, without adding a level shifter, in which logic gates such as inverter, NAND gate and NOR gate disposed at output terminals of functional blocks inside the chip, are used for changing levels of supply voltages.
It is another object of the present invention to provide a semiconductor device to which the logic interface circuit is applied.
To accomplish the first object, there is provided a logic interface circuit that comprises a logic gate means having pull up means and pull down means which respectively respond to one or more input signals to pull up and pull down an output terminal. It also includes reverse current preventing means connected between a first supply voltage and the pull up means for preventing current from reversing from the pull up means to the first supply voltage. In addition, a reverse current preventing and voltage boosting means is connected between the second supply voltage and the output terminal, for responding to the first supply voltage to turn off to prevent current from reversing from the output terminal to the second supply voltage if the first supply voltage is higher than the second supply voltage, and for responding to one or more input signals to turn on to set up the output terminal to the second supply voltage if the first supply voltage is lower than the second supply voltage.
In the preferred embodiment, a pre-charging means is connected in parallel to the reverse current preventing means for responding to the output signal generated from the output terminal to pre-charge a common point of the reverse current preventing means and the pull up means to the first supply voltage.
To accomplish the other object, there is provided a semiconductor device having a plurality of functional blocks and a plurality of memory cell array blocks, to which the logic interface circuit of the present invention is applied, the device comprising a logic interface circuit disposed between the functional blocks, some of which operate at the first supply voltage, and others of which operate at the second supply voltage, if different levels of supply voltages are applied to a plurality of functional blocks.


REFERENCES:
patent: 4039682 (1977-08-01), Dingwall et al.
patent: 5436585 (1995-07-01), DiMarco
patent: 5959902 (1999-09-01), Fontana et al.

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