Logic gate with matched output rise and fall times and method of

Details Logic gate with matched output rise and fall times and method of Logic gate with matched output rise and fall times and method of

1995-04-19

1995-12-26

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 95, 326121, H03K 19003

Patent

active

054791120

ABSTRACT:
A logic gate with highly matched output rise and fall times is provided which includes at least one stacked transistor pair (24) and at least one complementary stacked transistor pair (30) connected in parallel across at least one node (NODE 1 and NODE 2).

REFERENCES:
patent: 4507574 (1985-03-01), Seki et al.
patent: 4575648 (1986-03-01), Lee
patent: 4682055 (1987-07-01), Upadhyayula
patent: 4739195 (1988-04-01), Masaki
patent: 4749887 (1988-06-01), Sanwo et al.
patent: 4896059 (1990-01-01), Goodwin-Johansson

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