Logic gate cell

Details Logic gate cell Logic gate cell

1999-06-15

2001-12-11

Hoang, Huan (Department: 2818)

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

Field-effect transistor

C326S101000, C326S122000, C326S121000

Reexamination Certificate

active

06329845

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to logic gate cells used as an element in an LSI designed in a standard cell format and falls within the layout design technology of the logic gate cell manufactured in CMOS processes, and particularly to a logic gate cell featuring a small area and low power consumption.
2. Description of the Related Art
A cell having a circuit arrangement of two inverting logic gates connected is frequently used for a logic gate cell that is an element when an LSI is designed using a standard cell technology. The inverting logic gates here refer to a NAND gate, a NOR gate, a NOT gate, an AND-NOR compound gate and an OR-NAND compound gate. Logic symbols and circuit examples corresponding to the inverting logic gates are respectively shown in
FIGS. 1A and 1B
through
FIGS. 7A and 7B
.
FIGS. 1A through 7A
respectively show the logic symbols and
FIGS. 1B through 7B
respectively show the circuit examples thereof. Referring to a two-input AND gate as a typical example of these gates, the conventional art of the layout of the logic gate cell is now discussed.
The logic symbol of the two-input AND gate AND
2
is shown in FIG.
8
A and the two-input AND gate AND
2
is constructed by configuring an inverting logic gate NAND
2
and a NOT as shown in
FIG. 8B
, and an example of the circuit is shown in FIG.
9
.
FIG. 10
shows a conventional layout example of gate NAND
2
.
FIG. 11
shows diffusion regions and polysilicon wirings extracted from the layout shown in
FIG. 10
,
FIG. 12
shows first metal layer wirings extracted from the layout shown in
FIG. 10
, and
FIG. 13
shows second metal layer wirings extracted from the layout shown in
FIG. 10. A
diffusion region
501
for forming a P-type MOS transistor is arranged within a well
19
, and a diffusion region
502
for forming an N-type MOS transistor is arranged outside and below the well
19
. Transistors are formed at intersections where gate polysilicon wirings
503
intersect the diffusion regions
501
and
502
. P-type MOS transistors
31
to
33
shown in
FIG. 9
are formed side by side horizontally on the diffusion region
501
as shown in
FIGS. 10 and 11
, and N-type MOS transistors
34
to
36
shown in
FIG. 9
are formed side by side horizontally on the diffusion region
502
as shown in
FIGS. 10 and 11
. Squares shown in
FIG. 10
, FIG.
12
and
FIG. 13
represent contacts and via holes.
Available as methods of reducing the power consumption of LSIs through design effort of the logic gate cell are a technique to narrow a gate width of a transistor to reduce the power consumption in a transistor portion and a technique to reduce a layout area of the logic gate cell to reduce metal wiring length, and thus to reduce static capacitance of a metal wiring section, and both techniques are used in combination. Common techniques to promote a low power consumption are discussed in more detail in “Technical Paper of Low-Power LSI (Nikkei Micro Device Issue, Nikkei BP Company in Japan)”. In the gate AND
2
cell, to narrow the gate width of the transistor, the height of the diffusion regions
501
and
502
(the vertical length in
FIGS. 10 and 11
) should be small. The reduction in the height of the diffusion regions serves as a reduction in the cell height (the vertical length in FIG.
10
), and the cell area is accordingly reduced.
The above methods present the following problems. Firstly, when the cell height is lowered to reduce the cell area in the above methods, only the reduction in the height of the diffusion regions
501
and
502
contributes to lowering the cell height, and wiring areas other than the cell height and the spacing (a certain spacing is required in a region where the P-type changes to the N-type) between the diffusion region
501
and the diffusion region
502
are not reduced. As a result, as the cell area is reduced more, the area of the transistor portion gets smaller relative to the cell area, and the cell suffers a smaller area utilization. Secondly, as the cell height is lowered, there is no choice but to arrange a plurality of transistors horizontally side by side and connect them, to realize a high-power (wide gate width) transistor, and a horizontally elongated cell results, suffering a poor area utilization and the cell area, on the contrary, increases more than that in the high cell height layout. These problems arise as a result of attempting lower the cell height to reduce the cell area.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a high area-utilization and small-area logic gate cell which employs a layout that narrows a cell width (the horizontal length as shown in drawings) instead of lowering the cell height, to realize a low power consuming logic gate cell based on a narrow gate width transistor.
To layout a cell having the circuit arrangement of two inverting logic gates connected, firstly, the present invention employs a total of four diffusion regions, namely, two P-type MOS transistor diffusion regions and two N-type MOS transistor diffusion regions, and arranges them in four stages in a vertical direction in the drawings, rather than employing two diffusion regions as in the conventional art. Secondly, the two internal diffusion regions are used to realize a first inverting logic gate, and the two external diffusion regions are used to realize a second inverting logic gate that connects to the first inverting logic gate. Thirdly, wirings, which also serve as the metal wirings of an output portion of the second inverting logic gate, for interconnecting the P-type MOS transistor and the N-type MOS transistor, are partly or entirely formed of second metal layer wirings, and the second metal layer wirings extend over the second diffusion region and the third diffusion region.
In the above means, when the second inverting logic gate is realized using the two external diffusion regions, the wirings for interconnecting the P-type MOS transistor and the N-type MOS transistor are essentially required, and must be realized so that it may not interfere with the metal wirings of the first inverting logic gate constructed of the two internal diffusion regions. According to the present invention, taking advantage of the fact that the wirings for interconnecting the P-type MOS transistor to the N-type MOS transistor are limited to a single output portion, the wirings are realized by the second metal layer wirings, and the second metal layer wirings are arranged to extend over the first inverting logic gate so that no interference takes place therebetween as already described.
A logic gate cell having an even narrower gate width is provided by forming the first inverting logic gate output wirings of the first metal layer wirings, and by extending the second metal layer wirings of the output portion of the second inverting logic gate, over the first metal layer wirings. Specifically, since the first metal layer wirings of the output portion of the first inverting logic gate have no connection external to the cell, no problem is presented at all even if the second metal layer extends over the first inverting logic gate, and with the arrangement, the cell width is reduced to a minimum grid number required to route input and output terminals from within the cell.
In a portion of the input of the second inverting logic gate connected to the output of the first inverting logic gate, gate polysilicon wirings of the P-type MOS transistor and gate polysilicon wirings of the N-type MOS transistor are interconnected by the first metal layer wirings of the output portion of the first inverting logic gate. With the above arrangement, no particular wiring region is required as wirings for interconnection between the gates, and a logic gate cell having a narrow cell width is thus provided.
In addition to the above means, a gate width of the transistor formed in the external diffusion regions and used in the second inverting logic gate is set to be wider than a gate width of the transistor fo

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