Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-08-02
2011-08-02
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
07992062
ABSTRACT:
A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.
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Bassett Paul
Patel Prayag
Saint-Laurent Martin
Gaffin Jeffrey A
Kamarchik Peter M.
McMahon Daniel F
Qualcomm Incorporated
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