Logic compound method and logic compound apparatus

Details Logic compound method and logic compound apparatus Logic compound method and logic compound apparatus

2001-02-26

2003-08-19

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06609232

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a logic compound method and a logic compound apparatus using a register transfer level (RTL) description for a large-scale integrated (LSI) circuit including a plurality of subblocks.
In the recent development of LSI circuits, there has been broadly employed a design technique described, for example, in pages 36 to 43 of the “Design Wave Magazine” (May, 1999). Specifically, functional specifications of circuits necessary for a target LSI circuit are described in RTL notation to achieve logical compound according to the RTL description to obtain optimal gate levels for an actual production process of the LSI circuit.
The RTL description will be simply described.
FIG. 8
shows in a flowchart a processing flow of an LSI circuit development using an RTL description. The processing flow includes steps
81
to
84
.
Step
81
receives as an input thereto functions of a target LSI circuit designed in an RTL description at a higher abstraction level. Step
82
conducts logical compound using the contents of the RTL description to convert the RTL description into a gate net list optimized for an actual production process the LSI circuit.
Step
83
conducts allocation and wiring according to the gate net list to determine positions and wiring for the actual LSI circuit and resultantly generates a mask pattern. Step
84
produces the LSI circuit using the mask pattern.
Referring now to
FIGS. 9
to
13
, description will be given of the RTL description, a technology library, and compound restrictions as inputs to the logical compound processing, the gate net list as an output from the logical compound processing, and a logical compound operation using these items.
FIG. 9
shows an RTL description of a model circuit, i.e., circuit A. The respective lines have meanings as below.
Line
1
of
FIG. 9
represents a first point of definition of circuit A and includes a syntax rule of “module circuit-name (port list)”.
Lines
2
to
4
represent an input/output signal definition, an output signal definition, and an internal signal definition in the following syntax rules.
Line
2
: input input-signal-list;
Line
3
: output output-signal-list;
Line
4
: wire internal-signal-list;
Lines
5
to
7
describe combinations of circuits (combined circuits) as follows.
Line
5
: Description of inverter which inverts input “in” and outputs the inverted signal to i
1
Line
6
: Description of inverter which inverts input “in
2
” and outputs the inverted signal to i
3
Line
7
: Description of inverter which inverts input “in
4
” and outputs a resultant signal to out
Lines
8
to
11
describe a storage element, i.e., a flip-flop (FF) circuit. This flip-flop circuit has an input “in” and an output “out” and is synchronized with a rising edge of a clock signal clk.
Lines
12
to
15
similarly describe a storage element, i.e., a flip-flop circuit. This flip-flop circuit has an input “i
2
” and an output “out” and is synchronized with a rising edge of a clock signal clk.
Line
16
indicates an end of the circuit definition.
A compound restriction includes a circuit clock definition and an input/output delay (delay time) restriction. The compound restriction indicates delay targets of paths (signal paths between an input pin and a flip-flop circuit, between flip-flop circuits, and between a flip-flop circuit and an output pin) in the circuit to a logical compound tool.
FIG. 10
shows a concrete example of compound restrictions of circuit A. The values are represented in nanoseconds (ns).
For explanation, assume that
FIG. 11
shows a relationship between a circuit represented by the RTL description of FIG.
9
and the delay targets indicated by the compound restrictions of FIG.
10
.
Line
1
of
FIG. 10
is a clock definition which defines that a clock signal clk has a period of 10 ns. This gives a delay target
1101
indicating the logical compound tool to construct a circuit in which delay of a signal between flip-flop circuits synchronized with the clock clk is equal to or less than 10 ns.
Line
2
of
FIG. 10
is an input delay restriction. This indicates that a combined circuit
1111
having a delay of six nanoseconds exists between an external flip-flop circuit and the input port “in”. Therefore, this gives a delay target
1102
indicating the logical compound tool to construct a circuit in which delay of a signal from the input port “in” to the flip-flop circuit synchronized with the clock clk is 4 (=10−6) ns.
Line
3
of
FIG. 10
is an output delay restriction and means that a combined circuit
1112
with a delay of 1 ns exists between an output port “out” of the circuit and a flip-flop circuit synchronized with the clock clk. Therefore, this gives a delay target
1103
indicating the logical compound tool to construct a circuit in which delay of a signal from the flip-flop circuit synchronized with the clock clk to the output port “out” 9 (=10−1) ns.
A technology library is a table including functions and parameters of logical elements (to be referred to as cells herebelow) such as an AND element, an OR element, and a flip-flop element which can be generated in the LSI circuit production process.
FIG. 12
shows an example of the contents of the technology library.
First, the logical compound is achieved using the RTL description of circuit A shown in
FIG. 9
according to the compound restrictions of FIG.
10
. The results of the logical compound are then converted into a gate net including cells listed in the technology library shown in FIG.
12
.
FIG. 13
shows a gate net list resultant from the conversion.
In the gate net list shown in
FIG. 13
, lines
1
to
4
are the same as the RTL description of
FIG. 9
, namely, include a definition of a start point of module definition and definitions of input/output signals and internal signals.
Lines
5
to
9
of
FIG. 13
indicate a connection relationship and a description to instance a function of a technology library cell and are described in a syntax rule of
cell name instance-name (port list);
Line
10
indicates an end of the module definition.
Line
5
is obtained by instancing an inverter
1121
of the circuit in the RTL description of
FIG. 11
using an inverter invd
2
cell of the technology library of FIG.
12
. In the operation, the logical compound tool selects, according to the delay target
1102
that the delay from the input “in” to the input “i
1
” of the flip-flop element is 4 ns or less, invd
2
with a delay of 3 ns from the cells invd
0
to invd
3
having the same function in the technology library.
Line
6
is obtained by instancing an inverter
1122
of the circuit in the RTL description of
FIG. 11
using an inverter invd
0
cell of the technology library of FIG.
12
. In the operation, the logical compound tool selects, according to the delay target
1101
that the delay between the flip-flop elements is 10 ns or less, invd
0
with a smallest area among the cells invd
0
to invd
3
having the same function in the technology library.
As above, when a plurality of cells satisfy one delay target, the logical compound tool selects one of the cells having the smallest area among the cells.
Line
7
is obtained by instancing an inverter
1123
of the circuit in the RTL description of
FIG. 11
using an inverter invd
1
cell of the technology library of FIG.
12
. In the operation, the logical compound tool selects, according to the delay target
1103
that the delay between the flip-flop elements is 9 ns or less, invd
1
with a smallest area among the cells invd
0
and invd
1
having the same function in the technology library.
Lines
8
and
9
are obtained by instancing a flip-flop element in the RTL description of
FIG. 11
using a flip-flop element in the technology library of FIG.
12
.
As described above, the logical compound processing interprets the RTL description and replaces a description item of a flip-flop element with a cell of a flip-flop element in the technology library of the LSI circuit production process. For a combined circu

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