Logic circuitry and recording medium

Details Logic circuitry and recording medium Logic circuitry and recording medium

2011-07-19

2011-07-19

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S037000, C714S709000, C714S745000, C714S726000, C714S724000, C714S700000, C714S738000, C324S1540PB, C324S765010

Reexamination Certificate

active

07984350

ABSTRACT:
Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time.

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patent: 2004/0133825 (2004-07-01), Kobayashi
patent: 2004/0177299 (2004-09-01), Wang et al.
patent: 2007/0288822 (2007-12-01), Lin et al.
patent: 2008/0092093 (2008-04-01), Balakrishnan et al.
“A Novel Delay Fault Testing Methodology Using Low-Overhead Built-in Delay Sensor”, Ghosh et al., IEEE Transactions on Computer Design, vol. 25 No. 12, Dec. 2006.
“Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor”, Ghosh et al., IEEE International On-Line Testing Symposium, 0-7695-2620-9/06.
Paul H. Bardell, William. McAnney, Jacob Savir; “Built-In Test for VLSI: Pseudorandom Techniques”; Oct. 1987; pp. 23-24, Wiley-Interscience; USA.

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