Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-03-13
2000-07-11
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714741, 39550035, 39550036, G01R 3128, G06F 1100, G06F 1300
Patent
active
060888210
ABSTRACT:
A logic verification apparatus for a semiconductor integrated circuit classifies a program described in HDL into connection information of a synchronous circuit portion and connection information of a asynchronous circuit portion, converts a portion of the connection information of the asynchronous circuit portion into the connection information of the synchronous circuit portion and increases circuit portions the function of which can be verified by a cycle based simulation/static timing verification unit, thus making it possible to shorten the time for verification.
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patent: 5603015 (1997-02-01), Kurosawa et al.
patent: 5650938 (1997-07-01), Bootehsaz
patent: 5689683 (1997-11-01), Takasaki et al.
patent: 5841967 (1998-11-01), Sample et al.
Inoshita Toshinori
Inoue Yoshio
Mori Hiroyuki
Moriguchi Yasuo
Mitsubishi Denki & Kabushiki Kaisha
Moise Emmanuel L.
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