Logic circuit having gated clock buffer

Details Logic circuit having gated clock buffer Logic circuit having gated clock buffer

2011-05-31

2011-05-31

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S218000, C714S726000

Reexamination Certificate

active

07952390

ABSTRACT:
A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state, a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain, and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops.

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patent: 2002-323540 (2002-11-01), None

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