4. Electronic digital logic circuitry
  5. Clocking or synchronizing of logic stages or gates

Atsuo Takatori

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Delay fault test quality calculation apparatus, delay fault...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate

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Logic circuit having gated clock buffer

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2198600

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