Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-01
2004-11-02
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06813750
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The applicant is based upon and claims the benefit of priority from prior Japanese Patent Application P2001-103695, filed Apr. 2, 2001; the entire contents of which are incorporated by reference therein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic circuit design equipment and a method for designing a logic circuit. The present invention relates more particularly to a technology for reducing leakage current.
2. Description of the Related Art
As the voltage used for driving large scale integrated circuits has reduced in recent years, the threshold values (Vth) of transistors have increasingly been lowered. The lowering of the threshold values increases sub-threshold leakage current (hereinafter referred to as a leakage current). This leakage current flows during an active periods when the circuit is in operation, as well as during standby periods when circuit operation has been stopped.
As a technique to reduce such leakage current, Dual-Vth technology has been known. Dual-Vth technology is one in which both low Vth cells formed by low Vth transistors and high Vth cells formed by high Vth transistors are used in the same logic circuit. According to this technology, leakage current is reduced by use of high Vth cells with low speed operation on a path having some latitude with respect to timing. On the other hand, by the use of a low Vth cell with high speed operation, timing restriction of a path with tight timing can be fully and easily achieved, although this causes leakage current to increase.
In the logic circuit using Dual-Vth technology, the whole of an original logic circuit is constituted by, for example, low Vth cells first. Then, the logic circuit is constituted so as to reduce leakage current by substituting high Vth cells for low Vth cells on a path having latitude with respect to timing, as long as the timing allows. Here, there is a great difference between leakage currents even with in the same cell dependent on the state in which input to the cell. In spite of the difference between leakage currents, in the conventional method for designing the logic circuit, cell substitution has been performed irrespective of the state in which input to the cell. Accordingly, it is not always possible to produce a logic circuit displaying minimal leakage current.
The increase in leakage current that has accompanied microfabrication processing has been a problem in recent years. In such a logic circuit, mapping to integrate a plurality of logic gates into one logic gate has been performed in order to minimize the area and delay time, or in order to reduce leakage current itself. However, in such a case, the possibility that the difference in the leak currents in cells constituting the logic circuit may depend on the state in which input has not been considered. Accordingly, there is a problem that mapping to constitute a logic circuit showing minimum leakage current is not always performed.
Furthermore, in the recent appliances such as portable telephones and portable terminals, if leakage current during standby time were reduced it would be possible to greatly lengthen the life of a battery. Consequently, the development of a logic circuit showing a minimum possible leakage current during standby time is in demand.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a logic circuit design equipment has a state analysis section, a leakage current analysis section, and a cell substitution section. The state analysis section has a function of analyzing the input states of all of first cells, respectively. The leakage current analysis section has a function of analyzing the leakage currents of each of the first cells where each first cell is a high Vth cell showing a small leakage current at a low speed operation or a low Vth cell showing a large leakage current at a high speed operation, respectively. The cell substitution section has a function of substituting first cells for second cells within a range satisfying a timing restriction. Here, the threshold of second cells is different from the threshold of first cells.
According to a second aspect of the present invention, a logic circuit design equipment has a technology mapping section, a state analysis section, a leakage current analysis section, and a mapping selection section. The technology mapping section has a function of generating new logic circuits formed by mapping a plurality of logic gates constituting a logic circuit to one equivalent logic gate within a range satisfying a timing restriction. The state analysis section has a function of analyzing the input states of each of the new logic circuits, respectively. The leakage current analysis section has a function of calculating the leakage currents of each of the new logic circuits, respectively. The mapping selection section has a function of comparing the leakage currents of each of the new logic circuits with the others so as to select the new logic circuit in which leakage current is minimized.
According to a third aspect of the present invention, a method for designing a logic circuit includes analyzing the input states of all first cells respectively, analyzing the leakage currents of each first cells when each first cell is a high Vth cell showing a leakage current at a low speed operation or when each first cell is a low Vth cell showing a large leakage current at a high speed operation respectively, and substituting second cells for first cells within a range satisfying a timing restriction. Here, the threshold of second cells is different from the threshold of first cells.
According to a fourth aspect of the present invention, a method for mapping a logic circuit includes generating all new logic circuits constituted by mapping a plurality of logic gates which constitute a logic circuit to one equivalent logic gate within a range satisfying a timing restriction, analyzing the input states of each of the new logic circuits respectively, calculating the leakage currents of each of the new logic circuits respectively, comparing the leakage currents of each of the new logic circuits with the others, and selecting the new logic circuit in which leakage current is minimized.
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Usami et al., Automated Selective Multi-Threshold Design For Ultra-Low Standby Applications, Proceedings of the 2002 International Symposium on Low Power Electronics and Design, pp. 202-206, Aug. 2002.*
K. Usami et al., Low-Power Design Methodology and Applications Utilizing Dual Supply Voltages, Proceedings of the 2000 Conference on Asia and South Pacific Design Automation, pp. 123-128, Jan. 2000.*
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Kanazawa Masahiro
Kawabe Naoyuki
Kitahara Takeshi
Usami Kimiyoshi
Kabushiki Kaisha Toshiba
Thompson A. M.
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