Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1996-10-16
2000-08-08
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
39550002, G06F 1100, G06F 752
Patent
active
061016217
ABSTRACT:
A logic circuit with a pipelined structure has a plurality stage of combinational circuits and memory circuits such as flip-flops connected among the pipeline combinational circuits. The pipeline combinational circuits constituting a logic circuit is operated at a cycle time shorter than a signal propagation time for the critical path of the pipeline combinational circuit. For the case of activation of the path not covered by this cycle time, another combinational circuit and its peripheral circuits are additionally provided for generating a correction signal. Another combinational circuit has substantially the same logic. The cycle time is determined so as to cover the critical path including another combinational circuit. A comparator circuit compares an output signal of another combinational circuit and an output signal of the combinational circuit. If both the signals are not coincident, a selector is controlled to correct the signal by using the output signal of another combinational circuit.
REFERENCES:
patent: 4620292 (1986-10-01), Hagiwara et al.
patent: 4849921 (1989-07-01), Yasumoto et al.
patent: 4992969 (1991-02-01), Yamahata
patent: 4994996 (1991-02-01), Fossum et al.
patent: 5053987 (1991-10-01), Genusov et al.
patent: 5107453 (1992-04-01), Nomura
patent: 5111421 (1992-05-01), Molnar et al.
patent: 5126963 (1992-06-01), Fukasawa
patent: 5142685 (1992-08-01), Furui et al.
patent: 5377135 (1994-12-01), Kuroiwa
patent: 5548544 (1996-08-01), Matheny et al.
patent: 5568412 (1996-10-01), Han et al.
patent: 5694350 (1997-12-01), Wolrich et al.
patent: 5752061 (1998-05-01), Michiue
patent: 5784307 (1998-07-01), Sheaffer
patent: 5818745 (1998-10-01), Sheaffer
I. Unwala et al., "Superpipelined Adder Designs", IEEE Proceedings of the International Symposium on Circuits and Systems, (1993), pp. 1841-1844.
Beausoliel, Jr. Robert W.
Iqbal Nadeem
Kabushiki Kaisha Toshiba
LandOfFree
Logic circuit and method for designing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic circuit and method for designing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic circuit and method for designing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1160872