Logic built-in self test selective signature generation

Details Logic built-in self test selective signature generation Logic built-in self test selective signature generation

1999-05-12

2002-08-27

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06442723

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an improved Logic Built In self Test (LBIST) and more particularly to a LBIST system which facilitates the isolation of faults.
DOCUMENTS INCORPORATED HEREIN BY REFERENCE:
“Built-In Test for Complex Digital Integrated Circuits”, B. Könemann, J. Mucha, G. Zwiehoff, IEEE Journal of Solid State Circuits, Vol. SC-15 No. 3, pp. 315-318, June 1980. “Circular Self-Test Path: A Low-Cost Bist Technique”, Andrzej Krasniewski, Presented Jul. 7, 1987 at Princeton University. U.S. Pat. No. 4,071,902 to E. Eichelberger et al., U.S. Pat. No. 4,071,902. U.S. Pat. No. 5,150,366 to P. Bardell et al. Improving The Diagnostic Resolution of Built-in Test (IBM TDB1/Self-Test 88).
Diagnosis Using Parallel Superposition (IBM TDB7/85). Diagnosis of Self-Test Failures (IBM TDB2/84).
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. and Lotus is a registered trademark of its subsidiary Lotus Development Corporation, an independent subsidiary of International Business Machines Corporation, Armonk, N.Y. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
BACKGROUND
As will be appreciated by those skilled in the art, the design of electronic integrated circuit chips and devices has progressed, more and more circuitry is being disposed in increasingly dense patterns and it is becoming correspondingly more difficult to test and diagnose such circuits. One methodology for performing chip test is described in U.S. Pat. No. 4,071,902 issued to Edward Eichelberger, et al. on Jan. 31, 1978 and assigned to the same assignee as the present invention and incorporated herein by reference. This patent describes the basic features of a level sensitive scan design (LSSD) system. LSSD facilitates circuit testing and diagnostics. The circuits generally considered therein include digital circuits having logic and memory functions that are used in the design and construction of digital signal processing and information handling systems. Likewise here, integrated circuit devices of interest typically possess blocks of combinatorial logic whose inputs and outputs are supplied to certain memory elements. In particular, in an LSSD system the memory elements or circuits comprise shift register latches (SRLs). During test mode, these shift register latches can be logically reconfigured to operate as a shift register which is capable of providing logical inputs and storing logical output results and of moving or shifting these results into a storage register for comparison and analysis with known results.
LBIST designs employ a shift register sequence generator for generating pseudo-random bit sequences to be supplied to a plurality of shift register latch scan strings.
A prior art self-test system using MISR/Parallel SRSG called STUMPS is illustrated in FIG.
1
and is used to test integrated circuit chips and devices. The acronym SRSG stands for the Shift Register Sequence Generator. Such devices are typically implemented as linear feedback shift registers. These registers generally comprise a chain of shift register elements in which Exclusive-OR elements in a feedback loop are provided so as to combine several intermediate latch output signals which are returned to the shift register input. The feedback paths are configured to result in the generation of a pseudo-random sequence of binary digits which are employed as test sequences for the above mentioned combinatorial circuits. The design and construction of pseudo-random pattern generators in the form of linear feedback shift registers is well known in the art. Output signals from the SRSG are fed through channels to a plurality of different scan paths. Each scan path comprises a plurality of shift register latches. The output signals from the latch strings are supplied to signature register or MISR. It will be appreciated by those skilled in the art that the shift register latch elements also function in normal operation as sequential circuit memory elements in conjunction with combinatorial logic networks on, for example, a chip. The shift register latches function as memory elements between blocks of combinatorial logic. During operation of the circuit in normal system environment, the shift register latches function as memory elements passing signals to be processed from one combinatorial block to another and at the same time typically receiving input signals for subsequent application to combinatorial logic blocks in subsequent clock cycles. Thus the shift register latches play a significant role in establishing and defining stable logic outputs at appropriate points in a machine cycle. It is useful to keep in mind that the SRSG and the MISR are properly considered to be dedicated test elements. However, shift register latches serve a dual purpose which is more particularly apparent when considering the actual signal supplied to the shift register latches in normal operation.
Prior art response data compression techniques are very effective in reducing data volumes and test times, but as with any data compression scheme, some valuable information is lost. In the case of testing, this lost information consists of specific failing data required to diagnose the failing device and pinpoint the fault.
The current LBIST design and test methodology has evolved mainly in support of LSSD logic and structural testing. The STUMPS structure shown in
FIG. 1
illustrates a typical system and chip design that incorporates these concepts (see references) This LBIST structure incorporates a Liner Feedback Shift Register (LFSR) and a Multiple Input Signature Register (MISR). The LFSR serves as a pseudo random pattern generator that provides the stimuli for the logic being tested, while the MISR is utilized to generate a unique signature representing the responses from the logic. Ideally the signature for each failing device is different from the signature of a good device after a predefined number of test cycles.
The prior art LBIST test methodology is very effective in identifying defective devices in a high throughput manufacturing environment since it requires very little initialization data and expected signatures, but achieves a high level of fault average. Conversely, when the cause of the failure needs to be diagnosed and identified, the above test methodology encounters severe diagnostic problems.
The current diagnostic approach for the LBIST methodology is to subdivide the test into smaller intervals of test cycles and provide an expected good signature for each interval. The signature is then used during test to identify the failing interval. Of course this failing interval consists of many test cycles and expected responses, some of which pass and others of which fail some or all of the measurements. Once the failing interval has been identified one of two different diagnostic methods have been used in the past to resolve the failing vectors and failing responses for those vectors.
The first method is to retest the failing interval in a full data collection mode in order to log all the failing and passing measurements for each vector in the interval. A retest can be performed on-the-fly or as a diagnostic retest pass at a later time. In either case the amount of response data being collected is proportional to the number of test cycles in the signature interval and quickly becomes very large and unmanageable for cost effective manufacturing test systems.
The second method is to generate, after the initial test, corresponding deterministic patterns equivalent to those in the failing signature interval. These patterns can then be reapplied to the failing device in a second pass test to determine the failing responses. The problem with this later method is that it requires expensive deterministic test data generation and a second pass test to collect the failing data.
SUMMARY OF THE INVENTION
An object of this invention is the provision of additional built in functions to the existing LBI

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