Logic built-in self-test channel skipping during functional...

Details Logic built-in self-test channel skipping during functional... Logic built-in self-test channel skipping during functional...

2006-08-02

2008-12-30

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07472324

ABSTRACT:
A method and system for built-in self-testing architecture, including: a logic built-in self-test (LBIST) controller in operable communication with a pseudo-random pattern generator; a multiple input signature register in operable communication with a plurality of scan channels; and circuitry in operable communication with the pseudo-random pattern generator and the multiple input signature register, wherein the circuitry includes a channel skip function which allows selection of any combination of scan channels to skip while scanning.

REFERENCES:
patent: 5983380 (1999-11-01), Motika et al.
patent: 6370664 (2002-04-01), Bhawmik
patent: 6993694 (2006-01-01), Kapur et al.

Affiliated with

Also associated with

Rating

Logic built-in self-test channel skipping during functional... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic built-in self-test channel skipping during functional..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic built-in self-test channel skipping during functional... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4039745