Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-10-31
2010-12-14
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S715000, C714S724000, C714S727000, C714S728000, C714S729000, C714S006130, C714S025000, C714S030000, C714S032000, C714S719000, C714S720000, C714S735000, C714S818000, C714S824000, C716S030000
Reexamination Certificate
active
07853846
ABSTRACT:
A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.
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Cannon Stephen A.
Crouch Alfred L.
Dokken Richard C.
Winblad Gary A.
Holland & Hart LLP
Trimmings John P
Verigy (Singapore Pte. Ltd.
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