Local interconnects for improved alignment tolerance and size re

Details Local interconnects for improved alignment tolerance and size re Local interconnects for improved alignment tolerance and size re

1997-12-18

2000-09-19

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257383, 257411, 257760, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

061216631

ABSTRACT:
At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

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