Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-05
2001-07-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S598000, C438S618000, C438S740000
Reexamination Certificate
active
06258683
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the formation of local interconnects and semiconductor processing technology, and more particularly, to the reduction of junction leakage caused by the attack of a shallow trench isolation (STI) interface with silicon during contact etching
BACKGROUND OF THE INVENTION
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected. To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semiconducting regions (e.g. active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using local interconnects.
The local interconnect is typically a relatively low resistance material, such as a conductor or a doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of Tungsten (W), or other conductor, which is deposited within an etched opening, such as a via or a trench that connects the selected regions together. The use of local interconnects reduces the coupling burden of the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, as the density of the circuits increases there is a continuing need for more efficient, effective, and precise processes for forming smaller local interconnects.
A problem arises in the formation of a local interconnect due the relatively poor etch selectivity of an oxide dielectric material to the etch stop layer typically used to prevent over-etching into a diffusion region. The over-etching may lead to disconnection of the diffusion region at a field edge and result in a poor interconnection. Ibis may best be understood by reference to
FIGS. 1-3
to illustrate the concern.
FIG. 1
depicts a cross-section of a semiconnector device arrangement during one step of a local interconnect formation process. A silicon substrate
10
has polycrystalline silicon (hereafter polysilicon) gates
12
and
14
formed thereon. The polysilicon gate
14
is actually formed on the field oxide
16
. The spacer
15
(such as an oxide spacer) provides a shielding of the substrate
10
directly under the spacer
15
during implantation or diffusion of doping substrate
10
.
A plurality of silicide regions
18
are formed through conventional suicide techniques, for example, in a self-aligned silicide (“salicide”) technique. The material comprising the silicide regions
18
may be selected from different materials, such as titanium silicide, cobalt silicide, tungsten silicide, etc. silicide regions
18
provide a low resistant contact for the semiconductor devices.
The doped active region
20
is provided in the substrate
10
as defined by the doping. Typically, a heating step is performed to activate the dopants following the introduction of the dopants into the substrate
10
. The depth of the active region
20
in the substrate
10
is determined by the implantation energy employed to implant the dopant ions into the substrate
10
and the activation anneal.
An etch stop layer
22
is conformally deposited over the semiconductor wafer. An exemplary material for the etch stop layer is silicon oxynitride (SiON) and a conventional method of deposition is plasma-enhanced chemical vapor deposition (PECVD). The layer of dielectric material, such as, silicon dioxide derived from tetraethyl orthosilicate (TEOS), is deposited over the etch stop layer
22
and planarized. The dialectic layer
24
is then covered with a photoresist mask
26
which is patterned and developed with a desired local interconnect opening that is to be etched in the dielectric layer
24
. In this example of
FIG. 1
, the opening in the photoresist layer is positioned to provide a local interconnect opening in the dielectric layer
24
that will eventually connect the gate
14
of one device with an active region
20
of another device.
An etching step is then performed that etches through the dielectric layer
24
in accordance with the pattern in the photoresist layer
26
. It is desirable to stop this first etching step at the etch stop layer
22
. However, as depicted in
FIG. 2
, it often difficult to precisely stop the etch on the etch stop layer
22
, especially at the edge of the field
16
. In this circumstance, the local interconnect opening
28
undesirably extends into the substrate
10
at area
30
. The unintended etching through the etch stop layer
22
allows the etching to etch the silicide region
18
and the diffusion region
20
, creating the dip
30
into the substrate
10
.
As seen in
FIG. 3
, after the deposition of a liner (or “barrier layer”) that prevents diffusion of the conductive material into the other areas of the device, the local interconnect opening
28
is filled with a conductive material, such as tungsten
34
. However, the attack of the shallow trench isolation (STI) interface with the silicon during the contact etching leads to junction leakage. The junction leakage decreases the performance of the circuit, and in extreme circumstances, may cause circuit failure.
There is a need for an improved method of forming a local interconnect arrangement with a semiconductor device, and an improved method for performing the local interconnect arrangement with the semiconductor device to reduce or eliminate junction leakage.
SUMMARY OF THE INVENTION
This and other needs are met by the present invention which provides a method of forming a local interconnect comprising the steps of implanting ions in a semiconductor substrate to form active regions within the substrate. A dielectric layer is deposited over the substrate. The dielectric layer is then etched in accordance with a desired pattern to form a local interconnect opening. Additional ions are implanted within the semiconductor substrate to thereby enlarge the active regions. Conductive material is then deposited in a local interconnect opening.
By enlarging the active regions through implanting of additional ions within a semiconductor substrate, the junction depth can be increased so that it is deeper than the depth reached by the contact or local interconnect etch. Since the junction is deeper than the etch into the substrate, yield is increased and shorting of the device to the substrate is prevented.
The earlier stated needs are also met by another embodiment of the present invention which provides a local interconnect arrangement comprising a substrate layer, and a semiconductor device formed on the substrate. The semiconductor device has junctions formed within the substrate. A dielectric layer is provided on a substrate layer and on the semiconductor device. A local interconnect opening extends through the dielectric layer to the junctions, and conductive material fills this local interconnect opening. The junctions include a first set of ions implanted to a first depth into the substrate, as well as a second set of ions implanted to a second depth into the substrate. The second depth is greater than the first depth. The second depth is also greater than the depth of the local interconnect opening into the substrate.
The local interconnect arrangement of the present invention prevents a shorting of the device to the substrate, even if the contact etch has extended into the substrate more deeply than desired. This is because the second set of ions implanted to the second depth assures that the junction extends below the deepest part of the contact etch.
The foregoing and other features, aspe
Besser Paul
Chan Simon S.
Liu Yowjuang (Bill)
Advanced Micro Devices , Inc.
Jones Josetta
Niebling John F.
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