Local ground and V.sub.CC connection in an SRAM cell

Details Local ground and V.sub.CC connection in an SRAM cell Local ground and V.sub.CC connection in an SRAM cell

1996-05-20

1998-04-21

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438231, H01L 21336

Patent

active

057417350

ABSTRACT:
A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is formed within and proximate to the trench structure to electrically connect surface portions of the substrate to the buried layer. The buried layer is used to provide a voltage source to an integrated circuit. In one application, a P-type buried layer provides ground potential or V.sub.SS to a source region of an N-channel FET transistor. In a second application, an N-type buried layer provides supply potential or V.sub.CC to a source of a P-channel FET transistor.

REFERENCES:
patent: 4689871 (1987-09-01), Malhi
patent: 4933739 (1990-06-01), Harari
patent: 5378914 (1995-01-01), Ohzu et al.
Wolf et al., "Ion Implantation for VLSI," Silicon Processing for the VLSI Era-vol. 1; Lattice Press; Sunset Beach, CA, 1986; pp. 280-281.

Affiliated with

Also associated with

Rating

Local ground and V.sub.CC connection in an SRAM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Local ground and V.sub.CC connection in an SRAM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Local ground and V.sub.CC connection in an SRAM cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2057294