Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-10
2003-08-19
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06609233
ABSTRACT:
TECHNICAL FIELD
The technical field relates to timing analysis systems, and, in particular, to static timing analysis of a digital circuit.
BACKGROUND
A wide variety of design verification tools are required to produce a working integrated circuit from a functional specification. These tools analyze different parameters of a circuit design to insure that the circuit will function properly after the circuit is fabricated. One important set of verification tools includes timing analysis tools, which are widely used to predict the performance of very large scale integrated (VLSI) designs. Often, timing analysis determines the best path for a designer to pursue or helps to optimize the overall circuit design. In digital circuits, timing considerations can be critical to proper performance. Timing analysis tools may be either static or dynamic.
Dynamic timing analysis (DTA) tools provide the most detailed and accurate information obtainable concerning the performance of a circuit. With DTA, a design engineer must provide sets of waveforms to simulate the conditions under which a circuit will operate. This type of timing analysis is often generated through simulation of a circuit by simulation programs that operate at the transistor level. Examples of such circuit simulation programs are SPICE by University of California at Berkeley and ASTAP by IBM Corporation. For more information on SPICE, refer to “SPICE
2
: A Computer Program to Simulate Semiconductor Circuits,” by L. W. Nagel, Technical Report ERL-M520, UC-Berkeley, May 1975. These DTA programs typically operate by solving matrix equations relating to the circuit parameters, such as voltages, currents, resistances and capacitances. Additionally, such circuit simulation approaches to performance analysis are pattern dependent, or stated another way, the possible paths and the delays associated with the paths depend upon a state of a controlling mechanism or machine, of the circuit being simulated. Thus, the result of a DTA depends on the particular test pattern, or vector, applied to the circuit.
While such circuit simulation programs and DTA tools provide high accuracy, long simulation times are required because a large number of patterns must be simulated since the best and worst case patterns are not known before the simulation occurs. The number of simulations which must be performed is proportional to 2
n
, where “n” is a number of inputs to the circuit being simulated. Thus, for circuits having a large number of inputs, DTA is not always practical.
Static timing analysis (STA) tools are also widely used to predict the performance of VLSI designs. In STA, a design engineer applies stimulus only at each block input, not at base waveform. Additionally, each signal is assumed to switch independently in each machine cycle, i.e., static timing analyzer is waveform independent and simulates the most critical arrival time at each node in the circuit.
In STA, since only the best and worst possible rising and falling times are computed for each signal in the circuit, such times are typically determined in a single pass through a topologically-sorted circuit. When referring to a topologically-sorted circuit, a signal time associated with each subcircuit of the circuit being tested is determined in a sequential nature. Therefore, the signal time associated with a first subcircuit whose output will be propagated to a second subcircuit must be determined before the signal time associated with the second subcircuit is calculated. Typical static analysis methods are described in “Timing Analysis of Computer Hardware,” by Robert B. Hitchcock, Sr., et al., IBM J. Res. Develop., Vol. 26, No. 1, pp. 100-105 (1982).
Timing models used in timing analysis are blocks of computer data that can be used to recreate the timing behavior of an electronic circuit. The size of timing models should be as small as possible for a given complexity of circuit, while maintaining the accuracy of the timing model. In general, a smaller timing model will not only require less space in a computer memory, but also will be faster for a computer to evaluate. Often, timing model accuracy is sacrificed to shrink the timing model and speed its evaluation. This is especially important for large timing models that represent an entire subcircuit of an electronic system.
A popular technique for shrinking a timing model involves creating port-based timing models as opposed to path-based timing models. Port-based timing models analyze an electronic circuit to isolate and maintain only the timing behavior that can be observed at the circuit's connections, often referred to as ports, to surrounding circuits. Any timing behavior of a circuit that is internal to the circuit is discarded, leaving only the information that is essential to verifying the timing behavior of the circuit in the context of surrounding circuits. The port-based timing models have been used in both timing simulation and STA. The timing models are accurate, and generally provide good compression of timing model size.
In port-based timing modeling, the electronic circuit is analyzed to determine the longest time for an electronic signal to pass from each input port to each output port. Often the shortest time is determined as well. An edge triggered latch in the circuit, controlled by a clock signal, acts much like an internal port and is also considered a start point and an end point for electronic signals. At the instant the value of its clock signal changes, the edge triggered latch passes the value of its data signal to its output signal. At other times, the edge triggered latch holds the value of its output signal constant. Analysis is also done to determine the longest time for an electronic signal to pass from each input port to the input signals of each edge triggered latch and from the output signal of each edge triggered latch to each output port.
In true port-based timing models, the internal latch nodes are abstracted away and only the longest time for an electronic signal to arrive at each given output port is calculated. Often the shortest time is calculated as well. The latest (and often also the earliest) allowed time for signal to arrive at each given input port is also calculated. For circuits with edge triggered latches, these calculations are rather simple. The longest time for a signal to arrive at the output port is the time when the clock signal changes on the edge triggered latch that is connected to the output port by a combinational circuitry, plus the time the signal passes from the latch to the output port. If more edge triggered latches are connected to the output port by a combinational circuitry, the latest signal arrival from all the latches is considered. The latest allowed time for the signal to arrive at the input port is the time when the clock signal changes on the edge triggered latch that is connected to the input port by a combinational circuitry, minus the time the signal passes from the input port to the latch, minus the setup time for the latch (due to the physical characteristics of the latch electronic circuitry, the signal value at the latch input must be stable before the clock signal changes). If more latches are connected to the input port by a combinational circuitry, the latest time for the signal to arrive at the input port is the minimum from the latest times determined for the individual latches as described above. The latch that determines the minimum time is referred to as the most critical latch. PathMill's Black box timing model performs these calculations. However, the calculations become more complicated for circuits that use level triggered latches, and PathMill's Black box cannot model well such circuits.
Many digital circuits use level triggered latches, i.e., transparent latches, in place of edge triggered latches. Like an edge triggered latch, a level triggered latch is controlled by a clock signal. The edge triggered latches are active only at the instant the clock signal changes, while the level triggered latches can be active
Foltin Martin
Foutz Brian
Tyler Sean
Dinh Paul
Smith Matthew
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