Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2008-01-11
2011-10-18
Elmore, Stephen (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S203000, C711S156000
Reexamination Certificate
active
08041923
ABSTRACT:
What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.
REFERENCES:
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4972338 (1990-11-01), Crawford et al.
patent: 4992936 (1991-02-01), Katada et al.
patent: 5008811 (1991-04-01), Scalzi et al.
patent: 5058003 (1991-10-01), White
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 5553291 (1996-09-01), Tanaka et al.
patent: 5574873 (1996-11-01), Davidian
patent: 5617554 (1997-04-01), Alpert et al.
patent: 5790825 (1998-08-01), Traut
patent: 5845331 (1998-12-01), Carter et al.
patent: 6009261 (1999-12-01), Scalzi et al.
patent: 6308255 (2001-10-01), Gorshek, IV et al.
patent: 6418522 (2002-07-01), Gaertner et al.
patent: 6463582 (2002-10-01), Lethin et al.
patent: 6574706 (2003-06-01), Sutherland et al.
patent: 7120746 (2006-10-01), Campbell et al.
patent: 7197601 (2007-03-01), Slegel et al.
patent: 7234037 (2007-06-01), Errickson et al.
patent: 7490216 (2009-02-01), Chen et al.
patent: 7647589 (2010-01-01), Dobrovolskiy et al.
patent: 2002/0129085 (2002-09-01), Kubala et al.
patent: 2003/0056082 (2003-03-01), Maxfield
patent: 2004/0024953 (2004-02-01), Babaian et al.
patent: 2004/0098719 (2004-05-01), Smith et al.
patent: 2004/0230758 (2004-11-01), Slegel et al.
patent: 2004/0230768 (2004-11-01), Slegel et al.
patent: 2004/0230976 (2004-11-01), Slegel et al.
patent: 2005/0154855 (2005-07-01), Harris et al.
patent: 2005/0268071 (2005-12-01), Blandy et al.
patent: 2005/0289246 (2005-12-01), Easton et al.
patent: 2006/0036824 (2006-02-01), Greiner et al.
patent: 2006/0069899 (2006-03-01), Schoinas et al.
patent: 2007/0016904 (2007-01-01), Adlung et al.
patent: 2007/0028072 (2007-02-01), Hennessy et al.
patent: 2007/0101099 (2007-05-01), Shinohara et al.
patent: 2007/0124557 (2007-05-01), Kanai
patent: 2009/0037936 (2009-02-01), Serebrin
patent: 2009/0182964 (2009-07-01), Greiner et al.
patent: 2009/0182966 (2009-07-01), Greiner et al.
patent: 2009/0182971 (2009-07-01), Greiner et al.
patent: 2009/0182972 (2009-07-01), Greiner et al.
patent: 2009/0182973 (2009-07-01), Greiner et al.
patent: 2009/0182974 (2009-07-01), Greiner et al.
patent: 2009/0187724 (2009-07-01), Greiner et al.
patent: 2009/0187728 (2009-07-01), Greiner et al.
patent: 2009/0187732 (2009-07-01), Greiner et al.
patent: 2009/0193214 (2009-07-01), Greiner et al.
patent: 2009/0216992 (2009-08-01), Greiner et al.
patent: 2414842 (2005-12-01), None
International Search Report and Written Opinion dated Apr. 15, 2009 for PCT/EP2009/050227.
International Search Report and Written Opinion dated Apr. 9, 2009 for PCT/EP2009/050048.
“z/Architecture Principles of Operation, Chapter 10,” Internet Citation No. SA22-7832-06, Feb. 2008, XP002523174.
IBM, z/Architecture Principles of Operation, Apr. 2007, Sixth Edition, 1218 pges.
RW Marc and CE Schmaiz and RJ Shomler, Programmed Storage Utilization Measurement Technique, IBM Technical Disclosure Bulliten, Jun. 1973, Poughkeepsie NY.
JP Larner and RA Lassettre and ER Moore and BB Strickland, Channel DAT and Page Pinning for Block Unit Transfers, IBM Technical Disclosure Bulliten, Jul. 1980, Poughkeepsie NY.
JT Breslau and FC Greenstein and PG Rodell, Storage Key Protection At Object Level, IBM Technical Disclosure Bulliten, Dec. 1995, Cary NC.
IBM Corporation, “z/Architecture Principles of Operation”, XP002520423, Apr. 2007.
International Search Report and Written Opinion for PCT/EP2009/050050 dated Apr. 2, 2009.
International Search Report and Written Opinion for PCT/EP2009/050049 dated Apr. 7, 2009.
International Search Report and Written Opinion for PCT/EP2009/050048 dated Apr. 9, 2009.
International Search Report and Written Opinion for PCT/EP2009/050227 dated Apr. 15, 2009.
International Search Report and Written Opinion for PCT/EP2009/050051 dated Apr. 22, 2009.
International Search Report and Written Opinion for PCT/EP2009/050052 dated Apr. 23, 2009.
International Search Report and Written Opinion for PCT/EP2009/051864 dated May 27, 2009.
USPTO U.S. Appl. No. 11/972,705 to Dan F. Greiner et al., filed Jan. 11, 2008, entitled Dynamic Address Translation with Load Real Address, Non-Final Office Action dated Jul. 22, 2010.
USPTO U.S. Appl. No. 12/037,268 to Dan F. Greiner et al., filed Feb. 26, 2008, entitled Dynamic Address Translation with Translation Exception Qualifier, Non-final Office Action dated Nov. 3, 2010.
IBM System/370 Extended Architecture, Principles of Operation, Publication No. SA22-7085-1, Second Edition, Jan. 1987, 584 pages.
IBM, Power ISA, Version 2.03, Sep. 29, 2006, 850 pages.
The SPARC Architecture Manual, Version 9, 1994 SPARC International Inc., San Jose, CA., SAV09R1459912, ISBN: 0-13-825001-4, 399 pages.
Final Office Action, Date Mailed Jan. 16, 2011, U.S. Appl. No. 11/972,705, Greiner et al., filed Jan. 11, 2008.
Intel 53 and 1A-32 Aerchitectures Software Developer's Manual, vol. 3A, System Programming Guide part 1, 253668-036US. Sep. 2010, 842 pages http://www.intel.com/Assets/PDF/manual253668.pdf (hardcopy of manual submitted with U.S. Appl. No. 11/972,718, filed Jan. 11, 2008 to Dan F. Greiner et al.
Greiner Dan F.
Heller Lisa C.
Osisek Damian L.
Pfeffer Erwin
Sittmann Gustav E.
Campbell John E.
Elmore Stephen
Giardino, Jr. Mark A
International Business Machines - Corporation
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