Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-12
2006-12-12
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07149998
ABSTRACT:
A lithography process model is generated to account for asymmetric printing of a feature of a target pattern to help better predict how the target pattern will print. The process model for one embodiment may be generated based on data generated from measurements of spacings between symmetrically defined features of printed test patterns to help predict edge offsets of the feature relative to the target pattern when printed and/or to help predict a dimension of the feature when printed. The process model may be used to help design, manufacture, and/or inspect a mask to help print the target pattern more accurately and therefore help manufacture an integrated circuit (IC), for example, that more accurately matches its intended layout.
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Bever Hoffman & Harms LLP
Harms Jeanette S.
Siek Vuthe
Synopsys Inc.
Tat Binh
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