Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2008-08-20
2011-11-22
Chu, Chris (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257SE23021, C257S692000, C257S737000, C438S612000, C438S666000
Reexamination Certificate
active
08063497
ABSTRACT:
A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.
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Sun Wei-Hao
Tang Pao-Yun
Chu Chris
HannStar Display Corp.
Hsu Winston
Margo Scott
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