Link instruction register with instruction register, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S733000

Reexamination Certificate

active

08051349

ABSTRACT:
A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

REFERENCES:
patent: 5889788 (1999-03-01), Pressly et al.
patent: 6587979 (2003-07-01), Kraus et al.
patent: 6760874 (2004-07-01), Cote et al.
“Hierarchical test access architecture for embedded cores in an integrated circuit” by Bhattacharya,This paper appears in: VLSI Test Symposium, 1998. Proceedings. 16th IEEE Publication Date: Apr. 26-30, 1998 On pp. 8-14 ISBN: 0-8186-8436-4 INSPEC Accession No. 6039765.

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