Linear feedback shift register reseeding

Details Linear feedback shift register reseeding Linear feedback shift register reseeding

2006-12-26

2006-12-26

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S732000, C714S733000

Reexamination Certificate

active

07155648

ABSTRACT:
An apparatus has an integrated circuit that includes a seed register, a linear feedback shift register to load a test vector into a number of scan chains, and a signature register to receive a test response from the scan chains. The seed register, the linear feedback shift register, and the signature register each have the same register length. The linear feedback shift register and the signature register have the same shift frequency that is greater than a frequency at which a seed vector is loaded into the seed register. The linear feedback shift register is adapted to be selectively provided with bits to control a degree to which its vector is dependent on previous vectors. The scan chains may be configured as a single group providing a test response to a single input signature register or a set of groups providing a test response to a multiple input signature register.

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