Line edge roughness reduction for trench etch

Details Line edge roughness reduction for trench etch Line edge roughness reduction for trench etch

2005-09-27

2005-09-27

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S700000, C438S714000

Reexamination Certificate

active

06949460

ABSTRACT:
A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is etched into the dielectric layer with a dielectric to photoresist etch selectivity between 1:1 and 2:1.

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Calvin T. Gabriel, et al., “Measuring and Minimizing Line Edge Roughness in BEOL Damascene Dielectric Patterning”, 2003 AVS 4th Int'l. Conf. on Microelectronics and Interfaces, Mar. 3-6, Santa Clara, CA, pp. 204-207.

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