Line edge roughness reduction

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S637000, C438S689000, C438S694000, C438S717000, C257SE21256, C257SE21257

Reexamination Certificate

active

07459363

ABSTRACT:
A method for reducing line edge roughness comprises forming a masking structure on a substrate assembly, wherein the substrate assembly includes a number of layers. The method includes forming a layered masking structure by depositing a layer of material on the masking structure in order to reduce a line edge roughness (LER) of the masking structure, and etching a pattern of the layered masking structure into one or more of the number of layers of the substrate assembly before trimming the layered masking structure.

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Croon, J.A., et al., “Line Edge Roughness: Characterization, Modeling and Impact on Device Behavior”, Proceedings of the IEDM 2002, pp. 307-310.
Eeca, et al. “International Technology Roadmap for Semiconductors, 2001 edition”, http://public.itrs.net/Files/2001ITRS/Home.htm.
Leonardus, H.A., et al., “Influence of gate patterning on line edge roughness”, J. Vac. Sci. Tech. B21 (6), pp. 3140-3143 (Nov./Dec. 2003).

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