Line delay generator using one-port RAM

Details Line delay generator using one-port RAM Line delay generator using one-port RAM

1999-05-03

2003-05-27

Tung, Kee M. (Department: 2636)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Graphic display memory controller

C345S534000

Reexamination Certificate

active

06570572

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a line delay generator for delaying image data by temporarily storing it.
2. Description of Related Art
FIG. 9
is a block diagram showing a conventional line delay generator. In
FIG. 9
, the reference numeral
1
designates a controller that outputs an image data enable signal DENB by detecting the effective period of image data ID from a line synchronization signal LSYNC, and outputs a line reset signal LRST by detecting the ineffective period of the image data ID from the line synchronization signal LSYNC; and
2
designates a FIFO memory that loads the image data ID on a pixel by pixel basis in response to the image data enable signal DENB output from the controller
1
, and outputs first to m-th line delay data Q
1
-Qm. The FIFO memory
2
consists of m two-port FIFOs connected in cascade.
Next, the operation of the conventional line delay generator will be described.
The line delay generator generates line delay data by temporarily storing the image data. The example as shown in
FIG. 9
generates m line delay data with different delay times.
More specifically, the controller
1
monitors the signal level of the line synchronization signal LSYNC, and while the signal level is at the H (high) level, the controller
1
makes a decision that the current image data is effective, and supplies the FIFO memory
2
with the image data enable signal DENB.
In contrast, while the signal level of the line synchronization signal LSYNC is at the L (low) level, the controller
1
makes a decision that the current image data is ineffective, and supplies the FIFO memory
2
with the line reset signal LRST.
Then, as long as the controller
1
is outputting the image data enable signal DENB, the FIFO (
1
) of the FIFO memory
2
loads on a pixel by pixel basis the image data which is supplied in synchronization with an image clock signal ICLK, and simultaneously outputs the previously loaded image data as one-line delay data Q
1
.
Likewise, as long as the controller
1
is outputting the image data enable signal DENB, FIFO(
2
)-FIFO(m) of the FIFO memory
2
which are connected in cascade each load on a pixel by pixel basis the line delay data output from the previous FIFO, and output the previously loaded line delay data as two-line delay data Q
2
-m-line delay data Qm.
With the foregoing configuration, the conventional line delay generator can produce from the FIFO memory
2
the m line delay data Q
1
-Qm with different delay times. However, it has a drawback that the FIFO memory
2
becomes bulky because it consists of m two-port FIFOs connected in cascade to generate m line delay data.
On the other hand, Japanese patent application laid-open No. 5-135161/1993 discloses a technique that employs a single one-port DRAM instead of the FIFO memory consisting of m two-port FIFOs connected in cascade, thereby implementing a small line delay generator. However, it only discloses a technique that generates the line delay data by sequentially delaying the image data. It does not disclose a technique to output any of the delay line data during the write operation of one packet data, that is, to select any desired line delay data from among the one-line to m-line delay data stored in the one-port RAM. In addition, it does not disclose a technique to simultaneously output m line delay data with different delay times.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a line delay generator capable of reducing its packing area, and of producing any of the line delay data.
Another object of the present invention is to provide a line delay generator capable of simultaneously output a plurality of line delay data with different delay times.
According to a first aspect of the present invention, there is provided a line delay generator comprising: a packetizing circuit for packetizing image data to packet data; one port RAM for storing the packet data generated by the packetizing circuit; and a RAM controller for providing the one port RAM with a write command to write the packet data generated by the packetizing circuit, and with a read command to read any one or more packet data currently stored in the one port RAM.
Here, the RAM controller may provide the one port RAM with the read command to read the data currently stored in the one port RAM, and subsequently with the write command to write the packet data generated by the packetizing circuit.
The one port RAM may have a read/write bus with a width of 128 or more bits.
The packetizing circuit, the RAM controller and the one port RAM may be formed in one chip on a semiconductor substrate.
According to a second aspect of the present invention, there is provided a line delay generator comprising: a packetizing circuit for packetizing image data to packet data; one port RAM for storing the packet data generated by the packetizing circuit; a RAM controller for providing the one port RAM with a write command to write the packet data generated by the packetizing circuit, and with a read command to read packet data currently stored in the one port RAM; and an absorbing circuit for absorbing phase shift of the packet data read from the one port RAM.
Here, the RAM controller may provide the one port RAM with the read command to read the data currently stored in the one port RAM, and subsequently with the write command to write the packet data generated by the packetizing circuit.
The line delay generator may further comprise a processing circuit for processing the packet data whose phase shift is absorbed by the absorbing circuit, to generate processed image data.
The packetizing circuit may generate the packet data by packetizing the image data and the processed image data, and the absorbing circuit may split the packet data into the image data and the processed image data.
The line delay generator may further comprise a reprocessing circuit for reprocessing the processed image data split apart by the absorbing circuit.
The one port RAM may have a read/write bus with a width of 128 or more bits.
The packetizing circuit, the RAM controller, the one port RAM and the absorbing circuit may be formed in one chip on a semiconductor substrate.
The packetizing circuit, the RAM controller, the one port RAM, the absorbing circuit and the processing circuit may be formed in one chip on a semiconductor substrate.


REFERENCES:
patent: 5353402 (1994-10-01), Lau
patent: 6144362 (2000-11-01), Kawai
patent: 6370258 (2002-04-01), Uchida
patent: 5-135161 (1993-06-01), None
IEEE Computer Society proceedings international Conference on Computer Design VLSI in Computers and processors “Development of a high bandwidth merged logic/DRAM multimedia chip” by Luk et al, Conf Date Oct. 12-15, 1997, pp. 279-285.

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