Limited latch linehold capability for LBIST testing

Details Limited latch linehold capability for LBIST testing Limited latch linehold capability for LBIST testing

1998-01-22

2000-02-01

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060215143

ABSTRACT:
A method of LBIST testing of the entire chip logic whereby intermittent faults can be eliminated. LBIST control logic is programmed to apply linehold states to specified latches within the chip. Latches which feed logic that has intermittent faults can be held to a specified `0` or `1` state such that the intermittent faults causing intermittent signatures can be eliminated. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. The LBIST design contains logic for generating linehold controls that will apply a specified linehold state to selected latches during the scan operation portion of the LBIST test.

REFERENCES:
patent: 5383195 (1995-01-01), Spence et al.
patent: 5539753 (1996-07-01), Conner et al.
patent: 5661732 (1997-08-01), Lo et al.
patent: 5887004 (1999-03-01), Walther
IBM Journal of Research and Development, G322-0209-00. vol. 41, No. 4/5, Jul./Sep. 1997, pp. 611-627.

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