Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-10-15
2004-08-10
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S080000, C326S081000
Reexamination Certificate
active
06774673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to level shifters formed in a semiconductor integrated circuit for converting input signals having voltages to output signals having different voltages from the voltages of the input signals.
2. Description of the Related Art
In a semiconductor memory such as a DRAM or the like, the word lines for selecting memory cells are connected to the transfer transistors of the memory cells. In general, the high level voltages (boost voltages) of the word lines are set to a value higher than the power supply voltage so as to increase the amount of data that can be written into the memory cells and improve the data retention characteristics of the memory cells.
In this kind of DRAM, each of word decoders for selecting the respective predetermined word lines has: an address decoder for decoding an address signal supplied from the exterior of the DRAM; and a level shifter for converting the voltage of the decoded signal outputted from the address decoder to a boost voltage. Then, the boost voltage as converted by the level shifter is used as the high level voltage of the associated word line.
FIG. 1
shows an example of the level shifter formed in a word decoder.
The level shifter has: a switch
10
that is configured of an nMOS transistor and that receives a decoded signal DEC
1
; a voltage conversion circuit
12
that receives the decoded signal DEC
1
supplied via the switch
10
; and a CMOS inverter
14
that outputs, as a word line signal MWL, the decoded signal DEC
1
whose voltage level has been converted by the voltage converter circuit
12
.
The gate of the switch
10
is controlled by a control signal CNT. The control signal CNT is generated for use in common to a plurality of word decoders. The control signal CNT is generated from the decoded signal of an upper address signal and serves as a block selecting signal for selecting the plurality of word decoders. The high level of the control signal CNT is set to the power supply voltage, while the low level of the control signal CNT is set to the ground voltage. The decoded signal DEC
1
inputted to the switch
10
is the decoded signal of a lower address signal outputted by the word decoder.
The voltage conversion circuit
12
is configured of CMOS inverters
12
a
and
12
b
with their inputs and outputs connected together. The pMOS transistors of the voltage conversion circuit
12
have their sources connected to boost voltage lines VPP. The nMOS transistors of the voltage conversion circuit
12
have their sources connected to negative voltage lines VNWL.
The pMOS transistor of the CMOS inverter
14
has its source connected to a boost voltage line VPP. The nMOS transistor of the CMOS inverter
14
receives at its source a decoded signal DEC
2
, which exhibits the same logic and changes at the same timing as the decoded signal DEC
1
. The CMOS inverter
14
outputs to the associated word line a word line signal MWL of the same logic level as the decoded signal DEC
1
.
In the above described level shifter, when the decoded signal DEC
1
exhibits a low level (−0.5 V), the PMOS transistor of the CMOS inverter
12
a
is turned on and the nMOS transistor of the CMOS inverter
14
is turned on. At this moment, the nMOS transistor of the CMOS inverter
14
receives at its source a low level (−0.5 V) of the decoded signal DEC
2
. Accordingly, the CMOS inverter
14
outputs a low level (−0.5 V) of the word line signal MWL to the word line.
Contrarily, when the decoded signal DEC
1
exhibits a high level (the power supply voltage), the nMOS transistor of the CMOS inverter
12
a
is turned on and the pMOS transistor of the CMOS inverter
14
is turned on. At this moment, the pMOS transistor of the CMOS inverter
14
receives at its source the boost voltage VPP. Accordingly, the CMOS inverter
14
outputs to the word line a word line signal MWL whose voltage (VPP) is higher than the high level voltage of the decoded signal DEC
1
.
It should be noted that a negative voltage VNWL is being applied to the gate of the nMOS transistor of the CMOS inverter
12
a
, and hence the source-to-gate voltage of the pMOS transistor of the CMOS inverter
14
is increased. Accordingly, the on-resistance of the PMOS transistor of the CMOS inverter
14
is reduced, and hence the current supplied to the word line is increased.
There is a yearly increasing tendency that semiconductor integrated circuits, such as DRAMs and the like, are designed to use less power supply voltage so as to reduce the power consumption. In the level shifter shown in
FIG. 1
, the switch
10
for transmitting the decoded signal DEC
1
to the voltage conversion circuit
12
is configured of the nMOS transistor. The switch
10
, when receiving at its gate the high level of the control signal CNT (the power supply voltage), is turned on to transmit the voltage of the decoded signal DEC
1
to the voltage conversion circuit
12
. At this moment, the voltage conversion circuit
12
receives at its input the high level voltage having a value obtained by subtracting the threshold voltage of the nMOS transistor from the power supply voltage.
When the power supply voltage is low and the high level voltage of the input signal DEC
1
is low, the high level voltage supplied to the CMOS inverter
12
a
is also low. When the high level voltage supplied to the CMOS inverter
12
a
is lower than the threshold voltage of the nMOS transistor of the CMOS inverter
12
a
, this nMOS transistor cannot be turned on. Consequently, the level shifter cannot output a normal word line signal, resulting in a malfunction of the DRAM.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a level shifter that reliably operates even when the power supply voltage is low.
According to one of the aspects of the level shifter of the present invention, a first switch operates in accordance with a control signal and receives an input signal. A voltage conversion circuit converts the input signal, which has a voltage and is transmitted via the first switch, to an output signal having a different voltage from the voltage of the input signal, and outputs the output signal. A second switch connects an output node of the voltage conversion circuit to a voltage line corresponding with a voltage which the voltage conversion circuit should output in accordance with the input signal. For this reason, even when the voltage of the input signal falls outside the voltage range in which the voltage conversion circuit normally operates, for example, the voltage that the voltage conversion circuit should intrinsically output is supplied to the output node via the second switch. Thus, the voltage of the input signal can be converted without fail. As a result, the level shifter reliably operates even when the power supply voltage is low. In addition, the semiconductor integrated circuit incorporating such level shifters can be prevented from malfunctioning.
According to another aspect of the level shifter of the present invention, the first switch, voltage conversion circuit and second switch each includes at least one of pMOS transistors and nMOS transistors. The threshold voltages of the pMOS transistors are equal to each other, and/or the threshold voltages of nMOS transistors are equal to each other. In some conventional cases transistors having different threshold voltages are formed so as to increase the operation margin of a voltage conversion circuit so that the voltage conversion circuit operates without fail even when the power supply voltage is low. In such cases, the ion implantation amount has to be changed in accordance with the different threshold voltages of the transistors, which increases the number of the photo masks. The present invention, however, realizes sure conversion of the voltage of the input signal without changing the threshold voltages of the transistors, facilitating the layout design (mask design) of the level shifter.
According to another aspect of the level shifter of the present in
Okuyama Yoshiaki
Tsuboi Hiroyoshi
Arent & Fox PLLC
Tran Anh Q.
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