Level-restoring buffers for programmable interconnect...

Details Level-restoring buffers for programmable interconnect... Level-restoring buffers for programmable interconnect...

2008-04-07

2009-08-04

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S047000, C326S113000

Reexamination Certificate

active

07570079

ABSTRACT:
A technique that unfolds the nMOS-tree multiplexer to improve the propagation delay and/or active power consumption is provided. The main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge (with beneficial effects for power consumption). The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer.

REFERENCES:
patent: 7420389 (2008-09-01), Schmit et al.
patent: 2006/0132176 (2006-06-01), Lewis

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