Versatile bus interface macro for dynamically reconfigurable...

Details Versatile bus interface macro for dynamically reconfigurable... Versatile bus interface macro for dynamically reconfigurable...

2008-07-25

2009-11-17

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07619442

ABSTRACT:
Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial reconfiguration. The static module includes a signal interface. Each logic interface macro includes first pins coupled to the signal interface of the reconfigurable module and second pins coupled to the signal interface of the static module. The first pins and the second pins are disposed in an implementation area of the reconfigurable module. In one embodiment, each logic interface macro includes a slice of a configurable logic block (CLB). In some embodiments, each logic interface macro is implemented using another type of logic block, such as a block RAM and/or multiplier block.

REFERENCES:
patent: 5453706 (1995-09-01), Yee
patent: 5612891 (1997-03-01), Butts et al.
patent: 5734581 (1998-03-01), Butts et al.
patent: 5801547 (1998-09-01), Kean
patent: 5831448 (1998-11-01), Kean
patent: 6020758 (2000-02-01), Patel et al.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6211697 (2001-04-01), Lien et al.
patent: 6262596 (2001-07-01), Schultz et al.
patent: 6462579 (2002-10-01), Camilleri et al.
patent: 6754763 (2004-06-01), Lin
patent: 6798239 (2004-09-01), Douglass et al.
patent: 7024651 (2006-04-01), Camilleri et al.
patent: 7058919 (2006-06-01), Young et al.
patent: 7086025 (2006-08-01), Yang
patent: 7292063 (2007-11-01), Savage et al.
patent: 7337422 (2008-02-01), Becker et al.
patent: 7539848 (2009-05-01), Douglass et al.
Xilinx, Inc., “Virtex Series Configuration Architecture User Guide,” Application Note XAPP151 (v1.5), Sep. 27, 2000, pp. 1-45, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx, Inc., “Status and Control Semaphore Registers Using Partial Reconfiguration,” Application Note XAPP153 (v1.0), Jun. 7, 1999, pp. 1-4, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx, Inc., “Virtex-4 User Guide,” UG070 (v1.5), Mar. 21, 2006, pp. 163-185, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
U.S. Appl. No. 11/238,433, filed Sep. 28, 2005, Mason et al.

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