Level converting circuit for reducing an on-quiescence current

Details Level converting circuit for reducing an on-quiescence current Level converting circuit for reducing an on-quiescence current

1995-07-19

1996-10-15

Westin, Edward P.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 68, 326 34, H03K 190175

Patent

active

055657958

ABSTRACT:
A potential supplied to a first node from an inverter having an NMOS and a PMOS both series-connected between a constant potential node (V.sub.DD or GND) and the first node is switched according to a signal input to the inverter. The NMOS can be prevented from being brought into conduction beyond need, thereby making it possible to reduce an on-quiescence current.

REFERENCES:
patent: 4216390 (1980-08-01), Stewart
patent: 5117131 (1992-05-01), Ochi
patent: 5136189 (1992-08-01), Demaris
patent: 5304867 (1994-04-01), Morris
patent: 5406142 (1995-04-01), Nakama
patent: 5444392 (1995-08-01), Sommer

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