Leakage current reduction system and method

Details Leakage current reduction system and method Leakage current reduction system and method

2007-06-26

2007-06-26

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10982111

ABSTRACT:
An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.

REFERENCES:
patent: 5487074 (1996-01-01), Sullivan
patent: 5504756 (1996-04-01), Kim et al.
patent: 6622273 (2003-09-01), Barnes
patent: 6671841 (2003-12-01), Golshan
Abdollahai, A. and Fallah, F. and Pedram, M., “Leakage Current Reduction in Sequential Circuits by Modifying Scan Chains”,Proceedings of the 4thInternational Symposium on Quality Electronic Design(ISQED'03), 2003, IEEE.

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