Leakage and NBTI reduction technique for memory

Details Leakage and NBTI reduction technique for memory Leakage and NBTI reduction technique for memory

2011-08-09

2011-08-09

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189110, C365S226000

Reexamination Certificate

active

07995410

ABSTRACT:
In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.

REFERENCES:
patent: 4879690 (1989-11-01), Kenji et al.
patent: 5450365 (1995-09-01), Adachi
patent: 6038187 (2000-03-01), El Hajji
patent: 6501306 (2002-12-01), Kim et al.
patent: 6920060 (2005-07-01), Chow et al.
patent: 7000214 (2006-02-01), Iadanza et al.
patent: 7019559 (2006-03-01), Kouzuma
patent: 7098692 (2006-08-01), Joshi et al.
patent: 7120061 (2006-10-01), Daga
patent: 7245532 (2007-07-01), Jyouno et al.
patent: 7355905 (2008-04-01), Campbell et al.
patent: 7474571 (2009-01-01), Campbell
patent: 7652504 (2010-01-01), Campbell
patent: 2001/0008491 (2001-07-01), Sumimoto
patent: 2003/0206457 (2003-11-01), Hidaka
patent: 2004/0042334 (2004-03-01), Sasaki et al.
patent: 2004/0232944 (2004-11-01), Bu et al.
patent: 2005/0237099 (2005-10-01), Tachibana et al.
patent: 2006/0274587 (2006-12-01), Houston
patent: 2008/0123437 (2008-05-01), Agarwal et al.
U.S. Appl. No. 12/634,791, filed Dec. 10, 2009.
P.A. Semi, Inc. “The PWRficient Processor Family,” Jan. 2006, pp. 1-31.
“A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-K Metal Gate CMOS,” ISSCC 2008 / Session 13 / Mobile Processing / 13.1, 2008 IEEE International Solid-State Circuits Conference, 3 pages.
Heo, et al., “Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines,” The 29th Annual Int'l Symposium for COmputer Architecture (ISCA-29), Anchorage, AK, May 2002, 11 pages.
Office Action from U.S. Appl. No. 12/634,791, mailed Apr. 20, 2010.

Affiliated with

Also associated with

Rating

Leakage and NBTI reduction technique for memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Leakage and NBTI reduction technique for memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leakage and NBTI reduction technique for memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2730481