Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
1999-02-17
2001-02-20
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S698000, C257S700000, C257S707000
Reexamination Certificate
active
06191477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electronic packaging, and more particularly, to a leadless chip carrier design and structure.
2. Description of the Related Art
The microelectronics industry has continued to make significant advances in semiconductor device technology. Semiconductor devices are getting smaller, more dense, and run at higher speeds. However, as device sizes decrease and electrical components are moved closer together, one of the limiting properties of the semiconductor device is the electrical parasitics caused by resistance, capacitance and inductance effects. This is particularly troubling in radio frequency (RF) devices, where it is important to minimize electrical parasitics and to be able to predict their effects reliably. Also, the need to control device generated heat has become more critical as the speeds and power consumption of semiconductor devices has increased.
Controlling electrical parasitics is also important at the packaging level. The structure that supports the semiconductor device (i.e., chip) is commonly referred to as an electronic package. The electronic package is designed to provide electrical interconnection for I/O, signal lines, power supplies, and ground, in addition to environmental and physical protection.
One advantageous form of packaging is the chip carrier which is gaining in popularity. A big reason for this is that chip carriers are very small in size and thus make it possible to fit many devices on a substrate such as a printed circuit board (PCB) or ceramic. The package, as part of the completed semiconductor device, must be low in electrical parasitics and have good thermal dissipation. This is especially important for RF applications.
Electrical parasitics, particularly inductance, are some of the parameters that can adversely affect the performance of electrical packages. Inductance is thus one parameter that should be controlled and reduced. One of the factors contributing to the inductance is the long printed traces found in most packages. Another factor is the lack of a good ground plane located close to the device.
Present packages also have problems with dissipating heat. As semiconductor devices have increased in performance, their power requirements have also increased dramatically. Because of the large amount of power needed to operate a chip, the heat generated by a chip can reach several watts. Dissipation of this heat is an important design consideration of both the chip and chip carrier. Since the chip and chip carrier are made from different materials, each having a different coefficient of thermal expansion, they will react differently to the heat generated by the chip and the outside environment. The resulting thermal stresses can reduce the life of the semiconductor device by causing mechanical failures. Thus, it is desirable to be able to predict accurately the thermal effects of the chip carrier so that the chip carrier can be designed accordingly.
Therefore, there exists a need for a small package for a semiconductor device that would provide low electrical parasitics, predictable heat dissipation along with an efficient ground plane.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a semiconductor device is provided in the form of a chip carrier that includes a semiconductor chip attached to the upper surface of an interconnect substrate. A die attach pad is provided on the upper surface of the interconnect substrate and the chip is attached to this pad. On the lower surface of the substrate is a heat spreader positioned beneath the die attach pad. A plurality of vias extend through the thickness of the substrate from the upper surface to the lower surface. A first group of these vias is positioned to intersect both the die attach pad and the heat spreader. A second group of these vias is positioned apart from both the die attach pad and the heat spreader. Bonding pads are positioned to abut the second group of vias on the upper surface of the interconnect substrate. Device electrodes on the semiconductor chip are electrically coupled to these bonding pads by wire bonds. Electrically conductive lands are positioned to abut the second group of vias on the lower surface of the interconnect substrate and can be used to connect the semiconductor device to a printed circuit board or other electronic equipment.
REFERENCES:
patent: 5506755 (1996-04-01), Miyagi et al.
patent: 5640048 (1997-06-01), Selma
patent: 5646826 (1997-07-01), Katchmar
patent: 5721454 (1998-02-01), Palmer
patent: 5808873 (1998-09-01), Celaya et al.
patent: 5923084 (1999-07-01), Inoue et al.
patent: 6097089 (2000-08-01), Gaku et al.
patent: 2-058358 (1990-02-01), None
patent: 9-153679 (1997-11-01), None
patent: 10-313071 (1998-11-01), None
patent: 10-335521 (1998-12-01), None
1997, Fujitsu Presentation regarding BCC (Bump Chip Carrier) (25 pgs.).
Clark Sheila V.
Conexant Systems Inc.
Cruz Lourdes
Snell & Wilmer L.L.P.
LandOfFree
Leadless chip carrier design and structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Leadless chip carrier design and structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leadless chip carrier design and structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2573507