Leadframe package for semiconductor devices

Details Leadframe package for semiconductor devices Leadframe package for semiconductor devices

2003-03-13

2004-09-21

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With bumps on ends of lead fingers to connect to semiconductor

C257S670000, C257S666000

Reexamination Certificate

active

06794740

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor packages and, more particularly, to a leadframe which is adapted to provide improvements in the electrical and thermal performance and the assembly of packaging for transistor devices, such as MOSFET devices.
2. Description of the Related Art
As is known in the electrical arts, certain high power semiconductor devices are fabricated by forming a number of individual, low-power devices in a single semiconductor die or chip, and then “paralleling” such devices, i.e., connecting the individual devices together in parallel within the package of the device to define a single device capable of higher power output. One such device is known as a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor). MOSFETs and similar devices typically include a die body having a source terminal and a gate terminal disposed on the top surface thereof, and a drain terminal disposed on the bottom surface thereof. In prior art semiconductor packages such as MOSFETs, the source terminal is often connected to the leads of the leadframe of the semiconductor package through the use of multiple, parallel bonded wires. However, the use of such wires often contributes to various deficiencies in the performance of the semiconductor package, including relatively high electrical resistances, high parasitic source-inductance, and the formation of craters and voids in the die caused by the bonding of the wires.
In the prior art, it has been learned that most of the foregoing problems can be eliminated or reduced by replacing the large number of bonded wires from the source terminal of the MOSFET with a single, elongate conductive strap that facilitates the electrical connection of the source terminal to the source leads of the semiconductor package. However, this construction/assembly alternative also has been found to present certain problems. One such problem relates to the differences in the respective thermal coefficients of expansion of the materials of the strap, the semiconductor die (MOSFET), and leadframe. As a result of these differences, these parts experience different amounts of expansion and contraction with changes in the temperature of the semiconductor package. This relative movement of the respective parts causes large sheer stresses to develop in the attachment joints between them, which are typically lap joints of conductive adhesive or solder. These sheer stresses result in degradation of the electrical connection between the strap, die, and substrate and, in particular, in an unacceptably large change or shift in the critical drain-to-source resistance of the semiconductor die. The present invention addresses these deficiencies by providing a leadframe based semiconductor package for semiconductor devices, such as MOSFET devices, which is adapted to provide improvements in electrical and thermal performance. The structural attributes of the present invention and the advantages attendant thereto will be described in more detail below.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a semiconductor package comprising a leadframe which includes a die paddle having an opening formed therein. In addition to the die paddle, the leadframe includes a plurality of leads, at least one of which is disposed in spaced relation to the die paddle. The remaining leads are attached to the die paddle and extend therefrom. Electrically connected to the die paddle is the source terminal of a semiconductor die which also includes a gate terminal and a drain terminal. The gate terminal is itself electrically connected to at least one of the leads disposed in spaced relation to the die paddle. A package body at least partially encapsulates the die paddle, the leads, and the semiconductor die such that portions of the leads and the drain terminal of the semiconductor die are exposed in the package body.
Advantageously, the exposure of the drain terminal of the semiconductor die within the package body allows for the direct electrical connection thereof to an underlying substrate such as a printed circuit board. The source terminal of the semiconductor die may optionally be exposed within the package body of the semiconductor package as well for providing enhanced thermal performance or heat dissipation capability.
The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 2596993 (1952-05-01), Gookin
patent: 3435815 (1969-04-01), Forcier
patent: 3734660 (1973-05-01), Davies et al.
patent: 3838984 (1974-10-01), Crane et al.
patent: 4054238 (1977-10-01), Lloyd et al.
patent: 4189342 (1980-02-01), Kock
patent: 4258381 (1981-03-01), Inaba
patent: 4289922 (1981-09-01), Devlin
patent: 4301464 (1981-11-01), Otsuki et al.
patent: 4332537 (1982-06-01), Slepcevic
patent: 4417266 (1983-11-01), Grabbe
patent: 4451224 (1984-05-01), Harding
patent: 4530152 (1985-07-01), Roche et al.
patent: 4646710 (1987-03-01), Schmid et al.
patent: 4707724 (1987-11-01), Suzuki et al.
patent: 4737839 (1988-04-01), Burt
patent: 4756080 (1988-07-01), Thorp, Jr. et al.
patent: 4812896 (1989-03-01), Rothgery et al.
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4862246 (1989-08-01), Masuda et al.
patent: 4907067 (1990-03-01), Derryberry
patent: 4920074 (1990-04-01), Shimizu et al.
patent: 4935803 (1990-06-01), Kalfus et al.
patent: 4942454 (1990-07-01), Mori et al.
patent: 4987475 (1991-01-01), Schlesinger et al.
patent: 5029386 (1991-07-01), Chao et al.
patent: 5041902 (1991-08-01), McShane
patent: 5059379 (1991-10-01), Tsutsumi et al.
patent: 5065223 (1991-11-01), Matsuki et al.
patent: 5070039 (1991-12-01), Johnson et al.
patent: 5087961 (1992-02-01), Long et al.
patent: 5091341 (1992-02-01), Asada et al.
patent: 5096852 (1992-03-01), Hobson
patent: 5157480 (1992-10-01), McShane et al.
patent: 5168368 (1992-12-01), Gow, 3rd et al.
patent: 5172213 (1992-12-01), Zimmerman
patent: 5172214 (1992-12-01), Casto
patent: 5200362 (1993-04-01), Lin et al.
patent: 5200809 (1993-04-01), Kwon
patent: 5214845 (1993-06-01), King et al.
patent: 5216278 (1993-06-01), Lin et al.
patent: 5218231 (1993-06-01), Kudo
patent: 5221642 (1993-06-01), Burns
patent: 5250841 (1993-10-01), Sloan et al.
patent: 5252853 (1993-10-01), Michii
patent: 5258094 (1993-11-01), Furui et al.
patent: 5266834 (1993-11-01), Nishi et al.
patent: 5273938 (1993-12-01), Lin et al.
patent: 5277972 (1994-01-01), Sakumoto et al.
patent: 5278446 (1994-01-01), Nagaraj et al.
patent: 5279029 (1994-01-01), Burns
patent: 5294897 (1994-03-01), Notani et al.
patent: 5327008 (1994-07-01), Djennas et al.
patent: 5332864 (1994-07-01), Liang et al.
patent: 5335771 (1994-08-01), Murphy
patent: 5336931 (1994-08-01), Juskey et al.
patent: 5343076 (1994-08-01), Katayama et al.
patent: 5365106 (1994-11-01), Watanabe
patent: 5381042 (1995-01-01), Lerner et al.
patent: 5391439 (1995-02-01), Tomita et al.
patent: 5406124 (1995-04-01), Morita et al.
patent: 5410180 (1995-04-01), Fujii et al.
patent: 5414299 (1995-05-01), Wang et al.
patent: 5424576 (1995-06-01), Djennas et al.
patent: 5428248 (1995-06-01), Cha
patent: 5435057 (1995-07-01), Bindra et al.
patent: 5444301 (1995-08-01), Song et al.
patent: 5454905 (1995-10-01), Fogelson
patent: 5474958 (1995-12-01), Djennas et al.
patent: 5484274 (1996-01-01), Neu
patent: 5493151 (1996-02-01), Asada et al.
patent: 5508556 (1996-04-01), Lin
patent: 5517056 (1996-05-01), Bigler et al.
patent: 5521429 (1996-05-01), Aono et al.
patent: 5534467 (1996-07-01), Rostoker
patent: 5539251 (1996-07-01), Iverson et al.
patent: 5543657 (1996-08-01), Diffenderfer et al.
patent: 5544412 (1996-08-01), Romero et al.
patent: 5545923 (1996-08-01), Barber
patent: 5581122 (1996-12-01), Chao et al.
patent: 5592019 (1997-01-01), Ueda et al.
patent: 5592025 (1997-01-01), Clark et al.
patent: 5594274 (19

Affiliated with

Also associated with

Rating

Leadframe package for semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Leadframe package for semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Leadframe package for semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3272812