Leaded stacked packages having elevated die paddle

Details Leaded stacked packages having elevated die paddle Leaded stacked packages having elevated die paddle

2006-07-24

2009-02-24

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S676000, C257S723000

Reexamination Certificate

active

07495321

ABSTRACT:
A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having a lower lead and an elevated die paddle structure, attaching a first die to the elevated die paddle structure with a die adhesive (DA) for supporting the first die within the semiconductor package, and wire bonding the first die to the lower lead.

REFERENCES:
patent: 5012323 (1991-04-01), Farnworth
patent: 5633528 (1997-05-01), Abbott et al.
patent: 5777345 (1998-07-01), Loder et al.
patent: 4041224 (1992-07-01), None
patent: 0515094 (1992-11-01), None
patent: 1396886 (2004-07-01), None

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