Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2000-02-07
2003-06-24
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S666000
Reexamination Certificate
active
06583501
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to packaging for a semiconductor device, and more particularly to a crack inhibiting lead frame for a semiconductor integrated circuit. Conventional plastic semiconductor packages suffer from a failure mode referred to as “popcorn cracking.” This failure mode occurs in packages that are exposed to ambient moisture and are then heated to high temperatures, typically during reflow soldering.
The problem apparently arises because plastic IC packages have a tendency to absorb moisture from the environment. The moisture diffuses into the mold compound and other materials such as the chip attach material. During the solder reflow process, thermal vapor stresses developed at the chip attach material/die-pad interface or the mold compound/die-pad interface cause delamination to occur, especially at areas of high interfacial stress.
A conventional full pad design is shown in
FIGS. 10
,
10
A and
10
B where a chip or die
10
has its lower side
12
secured to a chip pad
14
by a chip attach material
16
. The chip attach
16
forms a fillet
18
between the side wall
20
of the chip
10
and the upper surface
22
of the chip pad
14
in an outer region known as the shoulder
24
. The pad
14
and attached chip
10
are thereafter encapsulated, or molded, in an encapsulation material
26
, for example epoxy, forming a package
30
in a known manner. In
FIG. 10A
, the package
30
is fabricated on a metal leadframe
31
. The package
30
includes wire bonds
37
.
Delamination of the chip
10
from the chip pad
14
and/or delamination of the die attach
16
from chip pad
14
can occur when the interfacial stresses exceed the interfacial strength. In particular, delamination often starts near the corner
32
of the chip
10
where the chip
10
meets the shoulder
24
. In the case of the full pad design shown, delamination can rapidly propagate over the entire pad area. This can cause the package
30
to crack from the outer edge
34
of the chip pad
14
where the cohesive strength of the mold compound
26
is exceeded. The resulting crack may propagate through the encapsulation
26
to the outer surface
36
of the package
30
. In a like manner, delamination of the chip pad
14
from the encapsulation material
26
can also act as a crack source resulting in a popcorn failure.
These problems necessitate storage of components in humidity controlled environments prior to reflow soldering. Such required storage procedures represent additional cost and uncertainty in product quality.
SUMMARY OF THE INVENTION
The invention is based upon the discovery that a lead frame for a crack resistant integrated circuit package has an isolated chip periphery support structure, including sidebars with inwardly extending chip contacting ears, and open crack-stop and delamination-stop areas therebetween. In a package utilizing the lead frame, the integrated circuit or chip is attached to the upper surface of the ears, and encapsulation material encloses and surrounds the frame and the chip. The encapsulation material bonds to a majority of the surface area of the chip and hardens to complete the package.
The invention provides a lead frame that reduces the popcorn failure that can occur during a solder reflow process. In an exemplary embodiment, this is achieved by reducing or minimizing the adhesive or attach material shoulder fillet, introducing crack-stop regions that interrupt the propagation of delamination or cracks and increasing the bonding surface area between the chip and encapsulation material.
In particular, the invention has two primary aspects. The first is that limiting the length of delamination failures limits the bending moment applied by water vapor evolved by heating water previously absorbed by the encapsulation material. By limiting bending moment, package flexure and consequent cracking are reduced. The second aspect of the invention reflects the discovery that the highest delamination stresses are concentrated in the shoulder region and at the comers of the chip. By moving the interfaces most vulnerable to delamination away from the chip comers, by minimizing shoulder regions, and by limiting the potential span of any delamination by reducing chip attach areas, the overall potential for popcorn cracking failure is reduced.
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Umehara, Norito et al., S-Pad Implementation; Total Plastic Package Crack Solution for Non-Moisture Sensitive Pakcage, New Package Development, Texas Instruments Japan, Ltd., Hi j. i. Plant, 4260 takao, Kawasaki, Hiji-machi, Hayami-gun Oita Japan 879-15.
Ganesan, Gans S. et al., Level I CrackFree Plastic Packaging Technology, Motorola Inc.. Semiconductor Products Sector, 2100 E. Elliot Road, Tempe, AZ 85284.
Nakazawa, Tsutomu et al., A Novel Structure to Realize Crack-Free Plastic Packages During Reflow Soldering Process-Development of Chip Side Support (CSS) Package, IEEE Transactions on Components Packaging and Manufacturing Technology—Pact C, vol. 19, No. 1, Jan. 1996, pp. 61-69.
Chan, K.C. and Chai, T.C., Type II Popcorn Failure Analysis in Plastic Encapsulated IC Package Using Scanning Acoustic Microscopy and Cross-Sectioning (not yet published).
Cha, Ki-Bon et al.; Ultra-Thin and Crack-Free Bottom Leaded Plastic (BLP) Package Design; LG Semicon (Gold Star) Package R&D Center, Cheongju, Korea 360-480 0569-5503/95/0000 ©1995 IEEE.
Camenforte Ray
Chai Tai Chong
Lim Thiam Beng
Neo Eric
Tan James
Clark Sheila V.
Dykema Gossett PLLC
Institute of Microelectronics
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