LDMOS with double LDD and trenched drain

Details LDMOS with double LDD and trenched drain LDMOS with double LDD and trenched drain

2011-03-01

2011-03-01

Monbleau, Davienne (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29256

Reexamination Certificate

active

07898026

ABSTRACT:
A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

REFERENCES:
patent: 2004/0262680 (2004-12-01), Ehwald et al.
patent: 2008/0246086 (2008-10-01), Korec et al.

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