LDMOS transistor with enhanced termination region for high...

Details LDMOS transistor with enhanced termination region for high... LDMOS transistor with enhanced termination region for high...

2007-04-24

2007-04-24

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S307000, C438S289000, C438S200000, C438S291000, C438S199000

Reexamination Certificate

active

11102173

ABSTRACT:
A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

REFERENCES:
patent: 5258636 (1993-11-01), Rumennik et al.
patent: 5633521 (1997-05-01), Koishikawa
patent: 2003/0141559 (2003-07-01), Moscatelli et al.

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