LDMOS and CMOS integrated circuit and method of making

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S276000

Reexamination Certificate

active

06818494

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of semiconductor integrated circuit devices, processes for making those devices and systems utilizing those devices. More specifically, the invention relates to a combined LDMOS and CMOS integrated circuit.
BACKGROUND OF THE INVENTION
CMOS (complimentary metal oxide semiconductors) integrated circuits are finding increased use in electronic applications such as printers. There are at least two important classes of transistor integrated circuits, low-voltage circuits in which the operating voltages are less than about six volts and high-voltage circuits in which the operating voltages are above about thirty volts. Moreover, the important difference in the two classes of transistors is that the high-voltage transistors require the channel region between the source and drain of the high-voltage transistor to be able to withstand a higher induced electric field without experiencing avalanche breakdown (punch through). As a consequence, the two classes of transistors have generally involved differences in structure, as well as differences in parameters. Such differences have dictated enough differences in processing that each class typically had been formed on its own separate integrated circuit (IC) rather than combined with the other class on a single IC.
Integrated circuit manufacturers have now incorporated high-voltage power MOSFET devices, such as a lateral double diffused MOS transistor (LDMOS) with CMOS control circuits to allow for versatility of design and increased reliability. This incorporation requires that relatively low-voltage CMOS logic circuits operate on the same die as a relatively high-voltage power transistor. While the incorporation has reduced total system costs, the fabrication of the combined CMOS and LDMOS transistors is still complex and expensive. In competitive consumer markets such as with printers and photo plotters, costs must continually be reduced in order to stay competitive and profitable. Further, the consumers expect increasingly reliable products because the cost of repair to the customers is often times higher than the cost of replacing the product. Therefore, to increase reliability and reduce costs, improvements are required in the manufacturing of integrated circuits that combine CMOS and LDMOS transistors.
SUMMARY
An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concentration that includes a first conductivity high-voltage transistor. In addition, the IC has a third well having a second dopant concentration of an opposite type than the first well that includes a first conductivity low-voltage transistor. The first conductivity low-voltage transistor and the second conductivity low-voltage transistor are created without a threshold voltage (V
t
) implant.


REFERENCES:
patent: 4325180 (1982-04-01), Curran
patent: 4628341 (1986-12-01), Thomas
patent: 5041895 (1991-08-01), Contiero et al.
patent: 5047358 (1991-09-01), Kosiak et al.
patent: 5508549 (1996-04-01), Watanabe et al.
patent: 5545577 (1996-08-01), Tada
patent: 5585294 (1996-12-01), Smayling et al.
patent: 5747850 (1998-05-01), Mei
patent: 5811850 (1998-09-01), Smayling et al.
patent: 5847432 (1998-12-01), Nozaki
patent: 5852314 (1998-12-01), Depetro et al.
patent: 5917222 (1999-06-01), Smayling et al.
patent: 6017797 (2000-01-01), Furukawa
patent: 6087232 (2000-07-01), Kim et al.
patent: 6111297 (2000-08-01), Grimaldi et al.
patent: 6127213 (2000-10-01), Tung
patent: 6144069 (2000-11-01), Tung
patent: 6267479 (2001-07-01), Yamada et al.
patent: 6576512 (2003-06-01), Taniguchi et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

LDMOS and CMOS integrated circuit and method of making does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with LDMOS and CMOS integrated circuit and method of making, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LDMOS and CMOS integrated circuit and method of making will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3352073

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.