LDD transistor using novel gate trim technique

Details LDD transistor using novel gate trim technique LDD transistor using novel gate trim technique

1998-07-17

2000-01-11

Chaudhuri, Olik

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438182, H01L 21336

Patent

active

060135700

ABSTRACT:
An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and the second mask layer are patterned to form first gate mask and second gate mask respectively. The polysilicon gate is then formed by anisotropically etching the polysilicon layer. The second gate mask is then removed. The polysilicon gate is then etched isotropically to reduce its width using the gate oxide layer and the patterned first gate mask as hard masks. The first gate mask is then used as a mask for dopant implantation to form source and drain extensions which are spaced away from the edges of the polysilicon gate. Thereafter, the first gate mask is removed and a spacer is formed dopant implantation to form deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the source and drain extension junctions and junctions, and the spacer is removed. Since the source and drain extension junctions are spaced away from the edges of the polysilicon gate, the displacement of the source/drain extension junctions into the channel is reduced. This results in a device with reduced parasitic capacitance.

REFERENCES:
patent: 4795718 (1989-01-01), Beitman
patent: 5001077 (1991-03-01), Sakai
patent: 5147814 (1992-09-01), Takeuchi
patent: 5286652 (1994-02-01), Wang et al.
patent: 5650342 (1997-07-01), Satoh et al.

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