Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-09-25
2000-08-08
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438226, 357360, 357355, H01L 218238
Patent
active
061001252
ABSTRACT:
An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted. The resistivity of those resistive LDD regions is greater than the resistivity of the adjacent portions of the drain region. The result is more uniform turn-on of ESD transistor fingers in a protection device set without the need to add valuable layout space and without increased processing steps.
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Hahn Daniel James
Harley-Stead Michael
Hulfachor Ronald Brett
Leibiger Steven
Atwood Pierce
Blum D S
Bowers Charles
Caseiro Chris A.
Fairchild Semiconductor Corp.
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